MFC2000 datasheet(133/426 Pages) ETC

133 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

5-7

5.1.6

Battery Backup and Prime Power Reset Registers

Name/Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Backup

Configuration

(BackupConfig)

$01FF8099

(Not Used) (Not Used) Internal

Power

Down

Select

Battery

Reset

Flag

Lockout

Time-out

Flag

SRAM

Enable

0 = disable

1 = enable

Bank 1

Data

interface

size:

0 = 8-bit

1 = 16-bit

Bank 0

Data

interface

size:

0 = 8-bit

1 = 16-bit

Rst. Value

xxx00000b

Read Value

00h

Name/Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Backup

Configuration

(BackupConfig)

$01FF8098

DRAM Backup Time

0 = no backup

1 = 1-2 days

2 = 2-3 days

3 = infinite days

Refresh

Rate

0 = normal

1 = slow

Oscillator

Speed

0 =

32.768

KHz

1 =

65.536

KHz

Bank 1

Enable

0 = disable

1 = enable

Bank 0

Enable

0 = disable

1 = enable

Bank 1

Interleave

Enable

0 = non

interleaved

1 = 2 way

interleaved

Bank 0

Interleave

Enable

0 = non

interleave

1 = 2 way

interleave

Rst. Value

00h

Read Value

00h

Battery during power down. When a time out condition occurs, the RASn and CASn signals are tristated. When

prime power has returned from a power down sequence, the user will have to perform a checksum on the DRAM

data to know if a time out has occurred since there is no indication that the DRAM battery has lost power. The

user will have to wait 1ms before accessing the DRAM after prime power has returned.

Bits 15-14:Not used

Bits 13:

Internal Power Down Select

0 = PWRDWNn is generated by or-ing power_down1 with

power_down2

1= PWRDWNn is generated by and-ing power_down1 with

power_down2

Note: Power_down1 and power_down2 are output signals from the power-down detection circuit

1 and 2.

Bit12:

Battery Reset Flag

This bit indicates that a BATRSTn occurred. To clear this bit, a 1 must

be written to this bit.

Bit11:

Lockout Time-out Flag

This bit indicates that a power down occurred, but no lockout was set

with in the 1-2 second period. The lockout timer initiated the

LOCKENn to create the lockout condition. Once the lockout condition

occurs, if the power down signal is high, the chip will come out of reset

after a PUD1 delay. To clear this bit, a 1 must be written to this bit.

Bit10:

SRAM Chip Select Enable

This bit enables the SRAM chip select CSN0.

Bit 9:

Bank 1 Interface Size

This register defines whether the databus to the bank 1 DRAMs is 8

bits wide or 16 bits wide. An 8-bit wide DRAM interface uses RASn[1]

and CASOn[0]. A 16-bit wide non-interleaved DRAM interface uses

RASn[1] and CASOn[1:0]. A 16-bit wide interleaved DRAM interface

uses RASn[1], CASEn[1:0], and CASOn[1:0].

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