AD6674 datasheet(36/97 Pages) AD

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Data Sheet

AD6674

Rev. C | Page 35 of 96

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) is calculated by

SNR = 20 × log 10(2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root

mean square of all jitter sources, including the clock input,

analog input signal, and ADC aperture jitter specifications. IF

undersampling applications are particularly sensitive to jitter

(see Figure 94).

100

1000

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

10 BITS

16 BITS

14 BITS

12 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

ANALOG INPUT FREQUENCY (MHz)

Figure 94. Ideal SNR vs. Analog Input Frequency and Jitter

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD6674. Separate

power supplies for clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

If the clock is generated from another type of source (by gating,

dividing, or other methods), retime it using the original clock at

the last step. See the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs.

Figure 95 shows the estimated SNR of the AD6674-1000 across

input frequency for different clock induced jitter values. The

SNR can be estimated by using the following equation:



























 











 

10log

(dBFS)

JITTER

ADC

SNR

INPUT FREQUENCY (Hz)

10M

100M

10G

25fs

50fs

75fs

100fs

125fs

150fs

175fs

200fs

Figure 95. Estimated SNR Degradation for the AD6674-1000 vs.

Input Frequency and Jitter

POWER-DOWN/STANDBY MODE

The AD6674 has a PDWN/STBY pin that can be used to

configure the device in power-down or standby mode. The

default operation is the PDWN function. The PDWN/STBY pin

is a logic high pin. When in power-down mode, the JESD204B

link is disrupted. The power-down option can also be set via

In standby mode, the JESD204B link is not disrupted and

transmits zeros for all converter samples. This can be changed

using Register 0x571[7] to select /K/ characters.

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