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AD6674 Datasheet(PDF) 31 Page - Analog Devices |
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AD6674 Datasheet(HTML) 31 Page - Analog Devices |
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31 / 97 page ![]() AD6674 Data Sheet Rev. C | Page 30 of 96 The recommended settings shown in Table 10 were used to collect the data while changing only the contents of Register 0x018. INPUT FREQUENCY (MHz) 50 55 60 65 70 75 80 85 90 10 60 110 160 210 260 310 360 410 460 1.5× 3.0× 4.5× Figure 77. Buffer Current Sweeps, AD6674-1000 (SFDR vs. Input Frequency and IBUFF); 10 MHz < fIN < 500 MHz; Front-End Network Shown in Figure 74 40 45 50 55 60 65 70 75 80 85 INPUT FREQUENCY (MHz) 503.4 677.6 851.9 1026.2 1200.5 1374.8 3.0× 4.0× 5.0× 6.0× Figure 78. Buffer Current Sweeps, AD6674-1000 (SFDR vs. Input Frequency and IBUFF); 500 MHz < fIN < 1500 MHz; Front-End Network Shown in Figure 74 40 45 50 55 60 65 70 75 80 INPUT FREQUENCY (MHz) 1513.4 1607.4 1701.5 1795.6 1889.8 4.5× 5.5× 6.5× 7.5× 8.5× Figure 79. Buffer Current Sweeps, AD6674-1000 (SFDR vs. Input Frequency and IBUFF); 1500 MHz < fIN < 2 GHz; Front-End Network Shown in Figure 74 In certain high frequency applications, the SFDR can be improved by reducing the full-scale setting, as shown in Table 10. At high frequencies, the performance of the ADC core is limited by jitter. The SFDR can be improved by reducing the full-scale level. 1.52GHz 1.65GHz 1.76GHz 1.9GHz 1.95GHz 55 60 65 70 75 80 55 60 65 70 75 80 –3 –2 –1 INPUT LEVEL (dBFS) 1.52GHz 1.65GHz 1.76GHz 1.9GHz 1.95GHz Figure 80. SNR/SFDR vs. Input Level and Input Frequencies, AD6674-1000 Figure 81, Figure 82, and Figure 83 show the SFDR vs. analog input frequency for various buffer settings for the AD6674-500. The recommended settings shown in Table 10 were used to take the data while changing the contents of register 0x018 only. 55 60 65 70 75 80 85 90 95 INPUT FREQUENCY (MHz) 1.5× 2.0× 2.5× 3.5× 4.5× Figure 81. Buffer Current Sweeps, AD6674-750 (SFDR vs. Input Frequency and IBUFF); 10 MHz < fIN < 450 MHz; Front-End Network Shown in Figure 74 INPUT FREQUENCY (MHz) 60 65 70 75 80 85 90 95 450.3 480.3 510.3 515.3 610.3 765.3 810.3 985.3 1010.3 4.5× 5.5× 6.5× 7.5× Figure 82. Buffer Current Sweeps, AD6674-750 (SFDR vs. Input Frequency and IBUFF); 450 MHz < fIN < 800 MHz; Front-End Network Shown in Figure 74 |
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