AD6674 datasheet(64/97 Pages) AD

64 / 97 page

Data Sheet

AD6674

Rev. C | Page 63 of 96

DIGITAL OUTPUTS

INTRODUCTION TO JESD204B INTERFACE

The AD6674 digital outputs are designed to the JEDEC Standard

No. JESD204B serial interface for data converters. JESD204B is

a protocol to link the AD6674 to a digital processing device

over a serial interface with lane rates of up to 12.5 Gbps. The

benefits of the JESD204B interface over LVDS include a reduction

in required board area for data interface routing, and enabling

smaller packages for converter and logic devices.

JESD204B OVERVIEW

The JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8B/10B encoding as well as

optional scrambling to form serial output data. Lane synchroniza-

tion is supported through the use of special control characters

during the initial establishment of the link. Additional control

characters are embedded in the data stream to maintain

synchronization thereafter. A JESD204B receiver is required to

complete the serial link. For additional details on the JESD204B

interface, users are encouraged to refer to the JESD204B

standard.

The AD6674 JESD204B data transmit block maps up to two

physical ADCs or up to eight virtual converters (when DDCs

are enabled) over a link. A link can be configured to use one,

two, or four JESD204B lanes. The JESD204B specification refers

to a number of parameters to define the link and these parameters

must match between the JESD204B transmitter (AD6674

output) and receiver (logic device input).

The JESD204B link is described according to the following

parameters:



L is the number of lanes per converter device (lanes per

link) (AD6674 value = 1, 2, or 4)



M is the number of converters per converter device (virtual

converters per link) (AD6674 value = 1, 2, 4, or 8)



F is the number of octets per frame (AD6674 value = 1, 2,

4, 8, or 16)



N΄ is the number of bits per sample (JESD204B word size)

(AD6674 value = 8 or 16)



N is the converter resolution (AD6674 value = 7 to 16)



CS is the number of control bits per sample (AD6674 value

= 0, 1, 2, or 3)



K is the number of frames per multiframe

(AD6674 value = 4, 8, 12, 16, 20, 24, 28, or 32 )



S is the number of samples transmitted per single converter

per frame cycle (AD6674 value = set automatically based

on L, M, F, and N΄)



HD is high density mode (AD6674 = set automatically

based on L, M, F, and N΄)



CF is the number of control words per frame clock cycle

per converter device (AD6674 value = 0)

Figure 123 shows a simplified block diagram of the AD6674

JESD204B link. By default, the AD6674 is configured to use two

converters and four lanes. Converter A data is output to

SERDOUT0±/SERDOUT1±, and Converter B is output to

SERDOUT2±/SERDOUT3±. The AD6674 allows other

configurations such as combining the outputs of both

converters onto a single lane or changing the mapping of the A

and B digital output paths. These modes are set up through a

quick configuration register in the SPI register map, along with

additional customizable options.

By default in the AD6674, the 14-bit converter word from each

converter is broken into two octets (eight bits of data). Bit 13

(MSB) through Bit 6 are in the first octet. The second octet

contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits

can be configured as zeros or a pseudorandom number (PN)

sequence. The tail bits can also be replaced with control bits

indicating an overrange, SYSREF±, signal monitor output, VDR

punish bits, or fast detect output. Control bits are filled and

inserted MSB first, such that enabling CS = 1 activates Control

Bit 2, enabling CS = 2 activates Control Bit 2 and Control Bit 1,

and enabling CS = 3 activates Control Bit 2, Control Bit 1, and

Control Bit 0.

The two resulting octets can be scrambled. Scrambling is

optional; however, it is recommended to avoid spectral peaks

when transmitting similar digital data patterns. The scrambler

uses a self synchronizing, polynomial-based algorithm defined

by the equation 1 + x14 + x15. The descrambler in the receiver

must be a self synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8B/10B encoder. The

8B/10B encoder works by taking eight bits of data (an octet) and

encoding them into a 10-bit symbol. Figure 124 shows how the

14-bit data is transferred from the ADC, the tail bits are added,

the two octets are scrambled, and the octets are encoded into

two 10-bit symbols. Figure 124 illustrates the default data format.

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