AD6674 datasheet(73/97 Pages) AD

73 / 97 page

AD6674

Data Sheet

Rev. C | Page 72 of 96

MULTICHIP SYNCHRONIZATION

The AD6674 has a SYSREF± input that allows the user flexible

options for synchronizing the internal blocks. The SYSREF±

input is a source synchronous system reference signal that

enables multichip synchronization. The input clock divider,

DDCs, signal monitor block, and JESD204B link can be

synchronized using the SYSREF± input. For the highest level of

timing accuracy, SYSREF± must meet setup and hold require-

ments relative to the CLK± input.

The flowchart in Figure 142 describes the internal mechanism

by which multichip synchronization can be achieved in the

AD6674. The AD6674 supports several features that aid users in

meeting the requirements for capturing a SYSREF± signal. The

SYSREF± sample event is defined as either a synchronous low to

high transition or a synchronous high to low transition. Addition-

ally, the AD6674 allows the SYSREF± signal to be sampled

using either the rising edge or falling edge of the CLK± input.

The AD6674 also has the ability to ignore a programmable

number (up to 16) of SYSREF± events. The SYSREF± control

options can be selected using Register 0x120 and Register 0x121.

AD6674 Datasheet(PDF) 73 Page - Analog Devices