PCI7620 datasheet(40/248 Pages) TI

40 / 248 page

2–19

Table 2–14. CardBus PC Card Interface Control Terminals

SOCKET A TERMINAL

SOCKET B TERMINAL

I/O

DESCRIPTION

NAME

NUMBER

NAME

NUMBER

I/O

DESCRIPTION

A_CAUDIO

B01

B_CAUDIO

C17

CardBus audio. CAUDIO is a digital input signal from a PC Card to the

system speaker. The PCI7x20 device supports the binary audio mode and

outputs a binary signal from the card to SPKROUT.

A_CBLOCK

B09

B_CBLOCK

J17

I/O

CardBus lock. CBLOCK is used to gain exclusive access to a target.

A_CCD1

B15

B_CCD1

N15

CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in

ith CVS1

d CVS2 t id

tif

d i

d i t

A_CCD1

A_CCD2

B15

C01

B_CCD1

B_CCD2

N15

C16

conjunction with CVS1 and CVS2 to identify card insertion and interrogate

cards to determine the operating voltage and card type.

A_CDEVSEL

A08

B_CDEVSEL

H18

I/O

CardBus device select. The PCI7x20 device asserts CDEVSEL to claim a

CardBus cycle as the target device. As a CardBus initiator on the bus, the

PCI7x20 device monitors CDEVSEL until a target responds. If no target

responds before timeout occurs, then the PCI7x20 device terminates the

cycle with an initiator abort.

A_CFRAME

E08

B_CFRAME

G18

I/O

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus

cycle. CFRAME is asserted to indicate that a bus transaction is beginning,

and data transfers continue while this signal is asserted. When CFRAME is

deasserted, the CardBus bus transaction is in the final data phase.

A_CGNT

E09

B_CGNT

H19

CardBus bus grant. CGNT is driven by the PCI7x20 device to grant a

CardBus PC Card access to the CardBus bus after the current data

transaction has been completed.

A_CINT

A02

B_CINT

B19

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request

interrupt servicing from the host.

A_CIRDY

F09

B_CIRDY

G19

I/O

CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator

to complete the current data phase of the transaction. A data phase is

completed on a rising edge of CCLK when both CIRDY and CTRDY are

asserted. Until CIRDY and CTRDY are both sampled asserted, wait states

are inserted.

A_CPERR

C09

B_CPERR

J13

I/O

CardBus parity error. CPERR reports parity errors during CardBus

transactions, except during special cycles. It is driven low by a target two

clocks following the data cycle during which a parity error is detected.

A_CREQ

F06

B_CREQ

E17

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card

desires use of the CardBus bus as an initiator.

A_CSERR

B02

B_CSERR

B18

CardBus system error. CSERR reports address parity errors and other

system errors that could lead to catastrophic results. CSERR is driven by the

card synchronous to CCLK, but deasserted by a weak pullup; deassertion

may take several CCLK periods. The PCI7x20 device can report CSERR to

the system by assertion of SERR on the PCI interface.

A_CSTOP

G09

B_CSTOP

J15

I/O

CardBus stop. CSTOP is driven by a CardBus target to request the initiator

to stop the current CardBus transaction. CSTOP is used for target

disconnects, and is commonly asserted by target devices that do not support

burst data transfers.

A_CSTSCHG

C03

B_CSTSCHG

A18

CardBus status change. CSTSCHG alerts the system to a change in the

card status, and is used as a wake-up mechanism.

A_CTRDY

C08

B_CTRDY

H13

I/O

CardBus target ready. CTRDY indicates the ability of the CardBus target to

complete the current data phase of the transaction. A data phase is

completed on a rising edge of CCLK, when both CIRDY and CTRDY are

asserted; until this time, wait states are inserted.

A_CVS1

A_CVS2

C04

E07

B_CVS1

B_CVS2

C18

F18

I/O

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2

are used in conjunction with CCD1 and CCD2 to identify card insertion and

interrogate cards to determine the operating voltage and card type.

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