PCI7620 datasheet(34/248 Pages) TI

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Table 2–8. PCI Interface Control Terminals

TERMINAL

I/O

DESCRIPTION

NAME

NUMBER

I/O

DESCRIPTION

DEVSEL

R08

I/O

PCI device select. The PCI7x20 device asserts DEVSEL to claim a PCI cycle as the target device. As a PCI

initiator on the bus, the PCI7x20 device monitors DEVSEL until a target responds. If no target responds before

timeout occurs, then the PCI7x20 device terminates the cycle with an initiator abort.

FRAME

W05

I/O

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus

transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted,

the PCI bus transaction is in the final data phase.

GNT

R02

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI7x20 device access to the PCI bus after

the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the

PCI bus parking algorithm.

IDSEL

V03

Initialization device select. IDSEL selects the PCI7x20 device during configuration space accesses. IDSEL can

be connected to one of the upper 24 PCI address lines on the PCI bus.

IRDY

U06

I/O

PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the

transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until

IRDY and TRDY are both sampled asserted, wait states are inserted.

PERR

U07

I/O

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR

when PERR is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4).

REQ

T01

PCI bus request. REQ is asserted by the PCI7x20 device to request access to the PCI bus as an initiator.

SERR

V07

PCI system error. SERR is an output that is pulsed from the PCI7x20 device when enabled through bit 8 of the

command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The PCI7x20 device

need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register,

this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.

STOP

W06

I/O

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus

transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support

burst data transfers.

TRDY

V06

I/O

PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the

transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until

both IRDY and TRDY are asserted, wait states are inserted.

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