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PCI7620 Datasheet(PDF) 7 Page - Texas Instruments

Part # PCI7620
Description  DUAL SOCKET CARDBUS AND SMART CARD CONTROLLER
PDF  248 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCI7620 Datasheet(HTML) 7 Page - Texas Instruments

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8.31
Link Control Register
8–28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.32
Node Identification Register
8–29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.33
PHY Layer Control Register
8–30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.34
Isochronous Cycle Timer Register
8–31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.35
Asynchronous Request Filter High Register
8–32
. . . . . . . . . . . . . . . . . . . . .
8.36
Asynchronous Request Filter Low Register
8–34
. . . . . . . . . . . . . . . . . . . . .
8.37
Physical Request Filter High Register
8–35
. . . . . . . . . . . . . . . . . . . . . . . . . .
8.38
Physical Request Filter Low Register
8–37
. . . . . . . . . . . . . . . . . . . . . . . . . .
8.39
Physical Upper Bound Register (Optional Register)
8–37
. . . . . . . . . . . . . .
8.40
Asynchronous Context Control Register
8–38
. . . . . . . . . . . . . . . . . . . . . . . .
8.41
Asynchronous Context Command Pointer Register
8–39
. . . . . . . . . . . . . .
8.42
Isochronous Transmit Context Control Register
8–40
. . . . . . . . . . . . . . . . . .
8.43
Isochronous Transmit Context Command Pointer Register
8–41
. . . . . . . .
8.44
Isochronous Receive Context Control Register
8–41
. . . . . . . . . . . . . . . . . .
8.45
Isochronous Receive Context Command Pointer Register
8–43
. . . . . . . .
8.46
Isochronous Receive Context Match Register
8–44
. . . . . . . . . . . . . . . . . . .
9
TI Extension Registers
9–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1
DV and MPEG2 Timestamp Enhancements
9–1
. . . . . . . . . . . . . . . . . . . . .
9.2
Isochronous Receive Digital Video Enhancements
9–2
. . . . . . . . . . . . . . .
9.3
Isochronous Receive Digital Video Enhancements Register
9–2
. . . . . . .
9.4
Link Enhancement Register
9–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5
Timestamp Offset Register
9–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 PHY Register Configuration
10–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1
Base Registers
10–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2
Port Status Register
10–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3
Vendor Identification Register
10–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4
Vendor-Dependent Register
10–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5
Power-Class Programming
10–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 Flash Media Controller Programming Model
11–1
. . . . . . . . . . . . . . . . . . . . . . . .
11.1
Vendor ID Register
11–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2
Device ID Register
11–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3
Command Register
11–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4
Status Register
11–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5
Class Code and Revision ID Register
11–5
. . . . . . . . . . . . . . . . . . . . . . . . . .
11.6
Latency Timer and Class Cache Line Size Register
11–5
. . . . . . . . . . . . . .
11.7
Header Type and BIST Register
11–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8
Flash Media Base Address Register
11–6
. . . . . . . . . . . . . . . . . . . . . . . . . . .
11.9
Subsystem Vendor Identification Register
11–7
. . . . . . . . . . . . . . . . . . . . . . .
11.10 Subsystem Identification Register
11–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.11 Capabilities Pointer Register
11–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.12 Interrupt Line Register
11–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.13 Interrupt Pin Register
11–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.14 Minimum Grant Register
11–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.15 Maximum Latency Register
11–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .



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