PCI7620 datasheet(49/248 Pages) TI

49 / 248 page

3–4

BIOS routine. For add-in card and docking-station/port-replicator applications, the PCI7x20 device provides a

two-wire inter-integrated circuit (IIC or I2C) serial bus for use with an external serial EEPROM.

The PCI7x20 device is always the bus master, and the EEPROM is always the slave. Either device can drive the bus

low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors on the SCL

and SDA signal lines. The PCI7x20 device is always the source of the clock signal, SCL.

System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and

SDA terminals. If the PCI7x20 device detects a logic-high level on the SCL terminal at the end of GRST, then it initiates

incremental reads from the external EEPROM. Any size serial EEPROM up to the I2C limit of 16 Kbits can be used,

but only the first 67 bytes (from offset 00h to offset 42h) are required to configure the PCI7x20 device. Figure 3–3

shows a serial EEPROM application.

In addition to loading configuration data from an EEPROM, the PCI7x20 I2C bus can be used to read and write from

other I2C serial devices. A system designer can control the I2C bus, using the PCI7x20 device as bus master, by

reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI

offset B3h, see Section 4.50) causes the PCI7x20 device to route the SDA and SCL signals to the SDA and SCL

terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the

serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h; see Sections

4.47, 4.48, and 4.49, respectively).

EEPROM interface status information is communicated through the serial bus control and status register (PCI offset

B3h, see Section 4.50). Bit 3 (SBDETECT) in this register indicates whether or not the PCI7x20 serial ROM circuitry

detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit 0

(ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM interface is

busy).

The subsystem vendor ID for functions 2 and 3 is also loaded through EEPROM. The EEPROM load data goes to

all four functions from the serial EEPROM loader.

SCL

SDA

VCC

SCL

SDA

PCI7x20

Serial

ROM

Figure 3–3. Serial ROM Application

3.4.5

Functions 0 and 1 (CardBus) Subsystem Identification

The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see

Section 4.27) make up a doubleword of PCI configuration space for functions 0 and 1. This doubleword register is

used for system and option card (mobile dock) identification purposes and is required by some operating systems.

Implementation of this unique identifier register is a PC 99/PC 2001 requirement.

The PCI7x20 device offers two mechanisms to load a read-only value into the subsystem registers. The first

mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the

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