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PCI7620 Datasheet(PDF) 33 Page - Texas Instruments |
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PCI7620 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 248 page  2–12 Table 2–7. PCI Address and Data Terminals TERMINAL I/O DESCRIPTION NAME NUMBER I/O DESCRIPTION AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 T02 P05 U01 U02 T03 P06 V02 U03 W03 U04 R06 V04 W04 U05 N07 V05 W07 U08 V08 N10 R09 V09 W09 V10 W10 R10 W11 V11 U11 N11 R11 W12 I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary-bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. C/BE3 C/BE2 C/BE1 C/BE0 W02 R07 P09 U10 I/O PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary-bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). PAR N09 I/O PCI-bus parity. In all PCI-bus read and write cycles, the PCI7x20 device calculates even parity across the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI7x20 device outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the PCI7x20 device compares its calculated parity to the parity indicator of the initiator. A compare error may result in the assertion of a parity error (PERR). |
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