PCI7620 datasheet(84/248 Pages) TI

84 / 248 page

4–7

4.9

Latency Timer Register

The latency timer register specifies the latency timer for the PCI7x20 device, in units of PCI clock cycles. When the

PCI7x20 device is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency

timer expires before the PCI7x20 transaction has terminated, then the PCI7x20 device terminates the transaction

when its GNT is deasserted.

Bit

Name

Latency timer

Type

Default

Latency timer

Offset:

0Dh

Type:

Read/Write

Default:

00h

4.10 Header Type Register

The header type register returns 82h when read, indicating that the PCI7x20 functions 0 and 1 configuration spaces

adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers 00h–7Fh, and

80h–FFh is user-definable extension registers.

Bit

Name

Header type

Type

Default

Header type

Offset:

0Eh (Functions 0, 1)

Type:

Read-only

Default:

82h

4.11 BIST Register

Because the PCI7x20 device does not support a built-in self-test (BIST), this register returns the value of 00h when

read.

Bit

Name

BIST

Type

Default

BIST

Offset:

0Fh (Functions 0, 1)

Type:

Read-only

Default:

00h

PCI7620 Datasheet(PDF) 84 Page - Texas Instruments

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