PCI7620 datasheet(17/248 Pages) TI

17 / 248 page

1–2

The PCI7x20 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external

clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which

generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock

signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal

is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data. Data bits

to be transmitted through the cable ports are received from the integrated LLC and are latched internally in

synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at

98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound

data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the

twisted-pair B (TPB) cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair

A (TPA) cable pair(s).

Function 3 of the PCI7620 and PCI7420 devices is a dedicated socket that supports SD, MMC, Memory Stick, and

Memory Stick-Pro cards. The Flash Media dedicated socket provides separate terminals for SD/MMC and Memory

Stick signals so that both an SD/MMC card and a Memory Stick/Memory Stick-Pro card can be used concurrently.

Various implementation specific functions and general-purpose inputs and outputs are provided through eight

multifunction terminals. These terminals present a system with options in PCI LOCK, serial and parallel interrupts,

PC Card activity indicator LEDs, and other platform specific signals. PCI-compliant general-purpose events may be

programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is

included for the general-purpose inputs and outputs.

The PCI7x20 device is compliant with the latest PCI Bus Power Management Specification, and provides several

low-power modes, which enable the host power system to further reduce power consumption.

The PCI7x20 device also has a three-pin serial interface compatible with both the Texas Instruments TPS2226 and

TPS2228 power switches. The TPS2226 or TPS2228 power switch provides power to the two CardBus sockets on

the PCI7x20 device. The power to each dedicated socket is controlled through separate power control terminals.

Each of these power control pins can be connected to an external 3.3-V power switch.

1.2

Features

The PCI7x20 device supports the following features:

•

PC Card Standard 8.0 compliant

•

PCI Bus Power Management Interface Specification 1.1 compliant

•

Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant

•

PCI Local Bus Specification Revision 2.3 compliant

•

PC 98/99 and PC2001 compliant

•

Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges

•

Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std

1394a-2000

•

Fully compliant with 1394 Open Host Controller Interface Specification 1.1

•

1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core VCC

•

Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

•

Supports PC Card or CardBus with hot insertion and removal

•

Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus

•

Supports serialized IRQ with PCI interrupts

•

Programmable multifunction terminals

PCI7620 Datasheet(PDF) 17 Page - Texas Instruments

PCI7620 Datasheet(HTML) 17 Page - Texas Instruments

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