PCI7620 datasheet(92/248 Pages) TI

92 / 248 page

4–15

4.25 Bridge Control Register

The bridge control register provides control over various PCI7x20 bridging functions. Some bits in this register are

global in nature and must be accessed only through function 0. See Table 4–7 for a complete description of the

Bit

Name

Bridge control

Type

Default

Bridge control

Offset:

3Eh (Function 0, 1)

Type:

Read-only, Read/Write

Default:

0340h

Table 4–7. Bridge Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

15–11

RSVD

These bits return 0s when read.

POSTEN

Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables the

posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst

cycles. Note that burst write data can be posted, but various write transactions may not. This bit is socket

dependent and is not shared between functions 0 and 1.

PREFETCH1

Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is

socket dependent. This bit is encoded as:

0 = Memory window 1 is nonprefetchable.

1 = Memory window 1 is prefetchable (default).

PREFETCH0

Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is

socket dependent. This bit is encoded as:

0 = Memory window 0 is nonprefetchable.

1 = Memory window 0 is prefetchable (default).

INTR

PCI interrupt – IREQ routing enable. This bit is used to select whether PC Card functional interrupts are

routed to PCI interrupts or to the IRQ specified in the ExCA registers.

0 = Functional interrupts are routed to PCI interrupts (default).

1 = Functional interrupts are routed by ExCA registers.

6 †

CRST

CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST

signal can also be asserted by passing a PRST assertion to CardBus.

0 = CRST is deasserted.

1 = CRST is asserted (default).

This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.

MABTMODE

Master abort mode. This bit controls how the PCI7x20 device responds to a master abort when the

PCI7x20 device is an initiator on the CardBus interface. This bit is common between each socket.

0 = Master aborts not reported (default).

1 = Signal target abort on PCI and signal SERR, if enabled.

RSVD

This bit returns 0 when read.

VGAEN

VGA enable. This bit affects how the PCI7x20 device responds to VGA addresses. When this bit is set,

accesses to VGA addresses are forwarded.

ISAEN

ISA mode enable. This bit affects how the PCI7x20 device passes I/O cycles within the 64-Kbyte ISA

range. This bit is not common between sockets. When this bit is set, the PCI7x20 device does not forward

the last 768 bytes of each 1K I/O range to CardBus.

CSERREN

CSERR enable. This bit controls the response of the PCI7x20 device to CSERR signals on the CardBus

bus. This bit is separate for each socket.

0 = CSERR is not forwarded to PCI SERR (default)

1 = CSERR is forwarded to PCI SERR.

† One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not

enabled, then this bit is cleared by the assertion of PRST or GRST.

PCI7620 Datasheet(PDF) 92 Page - Texas Instruments

PCI7620 Datasheet(HTML) 92 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL