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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.0

07-Apr-2017

CFR0011-120-00

42 of 54

Table 21: INTERFACE_CTRL 0x07

Bit

Mode

Symbol

Description

Reset

R/W

WRITE_MODE

2C write mode

0 = Page Write mode

1 = Repeated Write mode

0x0

R/W

PM_IF_HSM

Enables continuous High Speed mode on I

interface if asserted (no master code required)

0x0

R/W

PC_DONE

Asserted from Power Commander software after

the emulated OTP read has finished, automatically

cleared when leaving emulated OTP read

0x0

R/W

I2C_TO_EN

Enables automatic reset of I

2C interface when clock

stays low for > 35 ms

0: Disabled

1: Enabled

0x1

R/W

GPIO_0_DEGLITCH

0: Pad Deglitching disabled

1: Pad rejects pulses < 50 ns in duration

0x0

2:0

R/W

GPI_DEBOUNCE

GPI signal debounce time:

000: no debounce

001: 0.125 ms

010: 1.0 ms

011: 10 ms ( default )

100: 30 ms

101: 250 ms

110: 500 ms

111: 750 ms

0x3

Table 22: NONKEY_CTRL 0x08

Bit

Mode

Symbol

Description

Reset

7:6

R/W

SHUT_DELAY

Long press configuration at nONKEY for initiating a

power cycle:

00: Long press function disabled

01: KEY_DELAY + 4 s

10: KEY_DELAY + 5 s

11: KEY_DELAY + 6 s

0x0

5:4

R/W

KEY_DELAY

KEY_DELAY threshold at nONKEY

00: 1 s

01: 1.5 s

10: 2 s

11: 7 s

0x2

R/W

NONKEY_PIN

0: An E_nONKEY event is generated when the

debounced signal from port nONKEY goes low

(asserting edge). If not masked, an interrupt is

signaled to the host via nIRQ

1: An E_nONKEY event is generated when the

debounced signal from port nONKEY goes high

(de-asserting edge). If not masked, an interrupt is

signaled to the host via nIRQ

0x0

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