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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.0

07-Apr-2017

CFR0011-120-00

31 of 54

11.1 OFF Mode (HARDRESET)

DA9313 is in OFF mode without being supplied or with a low supply, when VO_VCORE ≤ VTH_LO_POR.

The only circuitry enabled is the VCORE regulator and its voltage supervision. The digital core is kept

reset in OFF mode.

When VO_VCORE ≥ VTH_HI_POR DA9313 transitions from OFF mode to ACTIVE mode or to

POWER_DOWN mode, depending on the AUTOBOOT setting.

11.2 POWER_DOWN Mode

The POWER_DOWN mode is the lowest quiescent current operating mode with a valid input voltage.

It can support a shelf mode for applications with integrated battery packs, which allows connecting

pre-charged batteries before the user enables the device for the first time.

PVC, oscillator, and analog references are disabled, only the nONKEY sense circuit is left running on

VCORE. A nONKEY wake press will transition the system to ACTIVE, see section 10.2.2.3.

11.3 ACTIVE Mode

ACTIVE mode is the main operating mode of DA9313 and is entered into after OTP load. The PVC is

then automatically turned on and operates in the configured mode.

NOTE

The host processor should wait for DA9313 to reach the ACTIVE mode following a start-up from OFF or

POWER_DOWN before starting the I

2C communication with DA9313, see Table 5 for timing details.

After the application starts up, the host processor should always read the FAULT_LOG register to

determine which one of the following sequences occurred before ACTIVE mode was enabled:

● from a fault condition (dedicated fault bit)

● from OFF during cold boot (POR bit)

● from power cycle due to long press of nONKEY

● from power cycle initiated via SOFTRESET write

● from power cycle initiated by PWC

11.4 SLEEP Mode

SLEEP mode is used to support application low power modes with lower quiescent current. The

mode can be entered into and exited from by register write or via GPI. An optional exit via nONKEY

is also supported when VDDIO has been disabled in SLEEP mode.

SLEEP mode is configurable via the SLEEP_CTRL register, see Table 13 for configuration options.

● To enter SLEEP mode via I2C, assert the SLEEP bit in the MODE_CTRL register.

● To enter SLEEP mode via GPI, configure GPIO_1_PIN or GPIO_0_PIN to SLEEP_EN. The level

of the GPI controls entry into SLEEP mode and exit back to ACTIVE mode.

ACTIVE configuration settings are re-applied on exit of SLEEP mode.

Table 13: SLEEP_CTRL Register Configuration

Control bit

Block

PVC_SL

PVC operation in SLEEP mode:

0: no change

1: automatic frequency mode

The PVC is changed to automatic frequency mode (variable frequency).

PVC_MODE setting is overwritten (old value restored at the exit of SLEEP

mode)

DA9313 Datasheet(PDF) 31 Page - Dialog Semiconductor

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