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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.0

07-Apr-2017

CFR0011-120-00

35 of 54

12 Control Interface

2C is always enabled in ACTIVE/SLEEP and IOs run on either VDDIO or VCORE, see section 11.7.

DA9313 can be software controlled through an I

2C serial control interface. Data are shifted into or out

of DA9313 under the control of the host processor that also provides the serial clock. In a normal

application case the interface is only configured once from OTP values, which are loaded during the

initial start-up of DA9313. In this phase the I

2C address is loaded from OTP.

The LOCK_REG register provides a software-controlled write protection (soft lock) of selected

registers from 0xE0 to 0x2F, the registers remain readable. This feature prevents malicious or

accidental writes to these critical registers from damaging the device. This soft lock is intended for

control by the system driver during device configuration on power up.

NOTE

The soft lock will reassert during all power cycles.

12.1 I

2C Communication

DA9313 has an OTP configurable device write address (default: 0xD0) and an OTP configurable

device read address (default: 0xD1). The 4 MSB of the I

2C device address can be OTP configured in

the register field IF_BASE_ADDR1.

The SCL port functions as the I

2C clock and the SDA port carries the bi-directional I2C data.

NOTE

SDA and SCL must be connected to GND if I

2C is not being used. The slave SDA and SCL must always be

connected to GND.

The I

2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be

pulled high by external pull-up resistors (2

kΩ to 20 kΩ range). The devices connected to the I

SDA can only drive the bus line low to ground. As a result two devices cannot conflict if they drive the

bus simultaneously. In Standard/Fast mode the highest frequency of the bus is 400 kHz. The exact

frequency can be determined by the application and does not have any relation to the DA9313

internal clock signals. DA9313 does not initiate any clock arbitration or slow down the clock. An

automatic I

2C reset can be triggered via control I2C_TO_EN if the clock signal stays low for more

than 35 ms.

The interface supports an operation compatible to Standard, Fast, Fast-Plus and High Speed mode

of the I

2C-bus specification Rev 4 [1]. The operation in High Speed mode at 3.4 MHz requires mode

changing in order to switch spike suppression and slope control characteristics compatible to the I

2C-

bus specification. The High Speed mode can be enabled on a transfer by transfer basis by sending

the master code (0000 1XXX) at the begin of the transfer.DA9313 does not make use of clock

stretching and delivers read data, without additional delay, up to 3.4 MHz.

Alternatively the interface can be configured to continuously use High Speed mode via PM_IF_HSM

(OTP configurable), so that the master code is not required at the beginning of every transfer. This

reduces the communication overhead on the bus but limits the attachable slaves to the bus to

compatible devices.

The communication on the I

2C bus always takes place between two devices, one acting as the

master and the other as the slave. The DA9313 will only operate as a slave.

The master or standalone device has stored the device address in register IF_BASE_ADDR1.

NOTE

When DA9313 is operating in master/slave mode, the I

2C bus is referenced to 4 V.

12.2 I

2C Control Bus Protocol

Data are transmitted over the I

2C bus in groups of 8 bits. To send a bit the SDA line is driven to the

intended state while the SCL is low (for example, a low on SDA indicates a zero bit). Once the SDA

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