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DA9313 Datasheet(PDF) 18 Page - Dialog Semiconductor |
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DA9313 Datasheet(HTML) 18 Page - Dialog Semiconductor |
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18 / 54 page  DA9313 High Efficiency Dual Cell Switched Capacitor Divider Datasheet Revision 3.0 07-Apr-2017 CFR0011-120-00 18 of 54 © 2017 Dialog Semiconductor 8 I 2C Control Bus Figure 6: I 2C Bus Timing Table 11: I 2C Control Bus Characteristics Unless otherwise noted, the following is valid for TJ = -40 ºC to +125 ºC Parameter Description Conditions Min Max Unit tBUF Bus free time from STOP to START condition 0.5 µs Cb Bus line capacitive load 150 pF Standard-mode / Fast-mode / Fast-mode Plus fSCL Clock frequency @ pin SCL 0 (Note 1) 1000 kHz tSU_STA START condition set-up time 0.26 µs tH_STA START condition hold time 0.26 µs tW_CL Clock LOW duration 0.5 µs tW_CH Clock HIGH duration 0.26 µs tR Rise time @ pin SCL and SDA Input requirement 1000 ns tF Fall time @ pin SCL and SDA Input requirement 300 ns tSU_D Data set-up time 50 ns tH_D Data hold time 0 ns High-Speed Mode fCLK_HS Clock frequency @ pin SCL 0 (Note 1) 3400 kHz tSU_STA_HS START condition set-up time 160 ns tH_STA_HS START condition hold time 160 ns tW_CL_HS Clock LOW duration 160 ns tW_CH_HS Clock HIGH duration 60 ns tR_HS Rise time @ pin SCL and SDA Input requirement 160 ns tF_HS Fall time @ pin SCL and SDA Input requirement 160 ns tSU_D_HS Data set-up time 10 ns tH_D_HS Data hold time 0 ns tSU_STO_HS STOP condition set-up time 160 ns Note 1 Maximum clock period is 38 ms if OTP control I2C_TO_EN is enabled. SDA SCL 70% 30% tF tR tBUF 70% 30% 1/fSCL tSU_STA tH_STA tW_CH tW_CL tR tF tH_D tSU_D tSP P S tSU_STO |
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