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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.0

07-Apr-2017

CFR0011-120-00

45 of 54

Table 28: PVC_CONFIG_1 0x0E

Bit

Mode

Symbol

Description

Reset

7:6

R/W

PVC_DROP

VDROP: drop from VBAT/2 at which VOUT, when

increasing and crossing (VBAT/2-VDROP) (so

becoming greater), generates a transition to DCM

00: 20 mV

01: 30 mV

10: 40 mV (default)

11: 50 mV

0x2

5:4

R/W

PVC_HYST

VHYST: hysteresis on the VDROP to go back to

CCM. So when VOUT is decreasing and crosses

(VBAT/2-VDROP-VHYST) (so becoming lower), it

generates a transition back to DCM.

00: 0 V

01: 10 mV

10: 20 mV (default)

11: 30 mV.

0x2

3:2

R/W

PVC_MS_DROP

Definition of four levels at which the master triggers

the slave request.

VMSI referenced to VCCM, where VCCM =

(VBAT/2-PVC_DROP-PVC_HYSTMAX):

00: 15 mV below VCCM

01: 30 mV below VCCM (default)

10: 45 mV below VCCM

11: 60 mV below VCCM

Note HYSTMAX is a constant value of 30 mV.

0x1

1:0

R/W

PVC_MS_HYST

MSI comparator hysteresis

00: 0 mV above VMSI

01: 15 mV above VMSI (default)

10: 30 mV above VMSI

11: 45 mV above VMSI

0x1

Table 29: PVC_CONFIG_2 0x0F

Bit

Mode

Symbol

Description

Reset

7:6

R/W

PVC_SLV_IF_PHASE

In master/slave configuration a clock is generated

to control the slave interface.

This clock has a configurable phase offset to the

PVC_CLOCK:

0: 0°

1: 90°

2: 180°

3: 270°

0x0

5:4

R/W

Reserved

0x1

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