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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.0

07-Apr-2017

CFR0011-120-00

37 of 54

S SLAVEadr W A

REGadr

SLAVEadr

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = No Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

7-bits

DATA

1-bit

8-bits

SLAVEadr

REGadr

SLAVEadr

7-bits

1-bit

8-bits

7-bits

DATA

1-bit

8-bits

DATA

8-bits

Figure 18: I

2C Page Read (SDA Line)

NOTE

The slave address after the Repeated START condition must be the same as the previous slave address.

Consecutive (page) write mode is supported if the master sends several data bytes following a slave

2C control block then increments the address pointer to the next I2C address,

stores the received data and sends an Acknowledge until the master sends the STOP condition.

SLAVEadr W A

REGadr

DATA

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = No Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

DATA

1-bit

8-bits

DATA

……….

8-bits

Repeated writes

Figure 19: I

2C Page Write (SDA Line)

An alternative write mode, alternating register address and data, can be configured via register bit

WRITE_MODE. Register addresses and data are sent alternately, see Figure 20, to support host

repeated write operations that access several non-consecutive registers. Data will be stored at the

previously received register address.

An update of WRITE_MODE cannot be done without interruption within a transmission frame. Thus,

if not previously selected or not set as OTP default, the activation of Repeated Write must be done

with a regular write on WRITE_MODE followed by a STOP condition. The next frame after a START

condition can be written in Repeated Write

SLAVEadr W A

REGadr

DATA

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = No Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

REGadr

1-bit

8-bits

DATA

……….

8-bits

Repeated writes

Figure 20: I

2C Repeated Write (SDA Line)

If a new START or STOP condition occurs within a message, the bus will return to IDLE-mode.

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