CCG3 datasheet(7/45 Pages) CYPRESS

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EZ-PD™ CCG3

Document Number: 002-03288 Rev. *J

Page 7 of 45

The I2C port on SCB 1-3 blocks of EZ-PD CCG3 are not

completely compliant with the I2C specification in the following

aspects:

■ The GPIO cells for SCB 1's I2C port are not overvoltage-tolerant

and, therefore, cannot be hot-swapped or powered up

independently of the rest of the I2C system.

■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of

0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a

VOL maximum of 0.6 V.

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the bus load.

Timer/Counter/PWM Block (TCPWM)

EZ-PD CCG3 has four TCPWM blocks. Each implements a

16-bit timer, counter, pulse-width modulator (PWM), and

quadrature decoder functionality.

GPIO

EZ-PD CCG3 has up to 20 GPIOs (these GPIOs can be

configured for GPIOs, SCB, SBU, and Aux signals) and SWD

pins, which can also be used as GPIOs. The I2C pins from SCB

0 are overvoltage-tolerant.

The GPIO block implements the following:

■ Seven drive strength modes:

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL)

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode)

■ Selectable slew rates for dV/dt related noise control to improve

EMI

During power-on and reset, the I/O pins are forced to the disable

state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed

I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

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