MP2935 datasheet(30/42 Pages) MPS

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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS

MP2935 Rev. 1.02

www.MonolithicPower.com

8/25/2015

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

VR_Rdy Signal

VRRDY pin is an active-high (open drain)

output that indicates that the start-up sequence

has completed and that the output voltage has

moved to the VBOOT value or the SVID

programmed VID value. This signal is part of the

start-up sequence for other voltage regulators,

the clock, microprocessor reset, etc. VRRDY

comparator monitors the operation of VR through

the fault latch logic. The signal remains asserted

during

normal

operation

and

de-asserts

whenever a fault (OCP, OVP, etc.) or shutdown

conditions occurred. This signal does not

represent DC output accuracy through its VID

value and does not track VID during dynamic VID

events. VRRDY indicates that the VR is

operating properly, not falsely trigger during

dynamic VID transitions.

VRReady_0V

flat

under

34h

configures multiple slaves (VRs) on the same

bus on the server platforms. It is also used in

notebook and desktop systems to program

VRRDY operation when the VID command is set

to 0V or off condition.

If “VR_RDY_0V” =0 (default, normal mode), then

VR_RDY de-asserts if the VR is given a SetVID

(0.0V) command, i.e., the VR is off.

If “VR_RDY_0V”=1, then VRRDY does not de-

assert when a SetVID (0.0V) command is issued.

This means that the 0V output is a valid voltage

setting and the VR is ready to accept the next

command. Under this definition, VR_RDY only

de-asserts

power-down

under

fault

conditions.

See Figure 8 for more details.

Figure 8: VR_RDY_0V Operation Waveforms

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