LTC2972 datasheet(60/112 Pages) LINER

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LTC2972

2972fa

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MFR_PG_CONFIG

The paged MFR_PG_CONFIG register defines the output operation of the per channel, open-drain, PG[1:0] pins.

Fault signals selected to propagate to the PG pins are independent of their associated fault response masking. The

VOUT overvoltage and VOUT undervoltage fast comparator signals are deglitched by the values set in the VOUT_OV_

FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE registers respectively, in addition to the deglitching set by the

MFR_PG_CONFIG register. Any programmed deglitching of the VOUT overvoltage and undervoltage signals will be

effectively disabled if the VOUT_EN signal is also propagated to PG[1:0] pins. During a power-on-reset, WDI reset, or

RESTORE_USER_ALL, the PG pins will pull low until the LTC2972 has completed its initialization and all NVM data

has been loaded into operating memory regardless of the MFR_PG_CONFIG register contents. The MFR_PG_CONFIG

pose outputs allowing the user to directly control the PG pin state with values written to the MFR_PG_GPO register.

The input pin state of the PG pins can be detected by reading the MFR_PADS register.

Figure 20. PG Output Pin Functional Block Diagram

PMBus COMMAND DESCRIPTION

VSENSEPn – VSENSEMn

PGn

VOUT_OV_FAULT_LIMIT

VOUT_UV_FAULT_LIMIT

DELAY FROM 0s TO

85.4s (TYP)

DEGLITCH FROM

0ms TO 100ms

DELAY FROM 0s TO

85.4s (TYP)

DEGLITCH FROM

0ms TO 100ms

TON MAX

VIN OV

VIN UV

TEMP OT

TEMP UT

VOUT_OV_FAULT_RESPONSE_DELAY

VOUT_UV_FAULT_RESPONSE_DELAY

MFR_PG_OV_UV_DEGLITCH

VOUT OV

VOUT UV

*SOME DETAILS OMITTED FOR CLARITY, ONLY ONE OF TWO CHANNELS SHOWN

VOUT_EN

OUTPUT

LOGIC

MFR_PG_OPERATION

MFR_PG_GPO_FORCE

2972 F20

LTC2972 Datasheet(PDF) 60 Page - Linear Technology

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