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LTC2972

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MFR_PG_GPO

The paged MFR_PG_GPO register defines the output logic state of the PG pins if Mfr_pg_operation equals 2'b00. This

MFR_PG_GPO Data Contents

BIT(S)

SYMBOL

OPERATION

b[7:1]

Reserved

Reserved, always returns 0

b[0]

Mfr_pg_gpo_force

1: Force PG Hi-Z

0: Force PG Low

MFR_PWRGD_EN

This command register controls the mapping of the watchdog and channel power good status to the PWRGD pin.

MFR_PWRGD_EN Data Contents

BIT(S) SYMBOL

OPERATION

b[15:9] Reserved

Read only, always returns 0s.

b[8]

Mfr_pwrgd_en_wdog Watchdog.

1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to determine

when the PWRGD pin gets asserted.

0 = Watchdog timer does not affect the PWRGD pin.

b[7:2] Reserved

Always returns 000000b.

b[1]

Mfr_pwrgd_en_chan1 Channel 1.

1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when

the PWRGD pin gets asserted.

0 = PWRGD status for this channel does not affect the PWRGD pin.

b[0]

Mfr_pwrgd_en_chan0 Channel 0.

1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when

the PWRGD pin gets asserted.

0 = PWRGD status for this channel does not affect the PWRGD pin.

MFR_POWERGOOD_ASSERTION_DELAY

This command register allows the user to program the delay from when the internal power-good signal becomes valid

until the PWRGD pin output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal

oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value

of this command always returns what was last written and does not reflect internal limiting.

The PWRGD pin de-assertion delay and threshold source is controlled by Mfr_config_all_pwrgd_off_uses_uv. Sys-

tems that require a fast PWRGD pin de-assertion should set Mfr_config_all_pwrgd_off_uses_uv = 1. This uses the

VOUT_UV_FAULT_LIMIT and the high speed comparator to de-assert the PWRGD pin. Systems that require a separate

power good off threshold should set Mfr_config_all_pwrgd_off_uses_uv = 0. This uses the slower ADC polling loop

and POWER_GOOD_OFF to de-assert the PWRGD pin.

PMBus COMMAND DESCRIPTION

LTC2972 Datasheet(PDF) 62 Page - Linear Technology

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