CS5530A datasheet(182/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

SMI Source is a VGA Timer Event (Read to Clear): SMI was caused by the expiration of the VGA Timer (F0 Index 8Eh)?

0 = No; 1 = Yes.

SMI generation enabling is at F0 Index 83h[3].

SMI Source is Video Retrace (IRQ2) (Read to Clear): SMI was caused by a video retrace event as decoded from the

serial connection (PSERIAL register, bit 7) from the GX1 processor? 0 = No; 1 = Yes.

SMI generation enabling is at F0 Index 83h[2].

4:2

Reserved (Read to Clear): Always reads 0.

SMI Source is Audio Interface (Read to Clear): SMI was caused by the audio interface? 0 = No; 1 = Yes.

The next level SMI status registers is found in F3BAR+Memory Offset 10h/12h.

SMI Source is Power Management Event (Read to Clear): SMI was caused by one of the power management resources?

0 = No; 1 = Yes.

The next level of status is found at F0 Index 84h-87h/F4h-F7h.

Note: The status for the General Purpose Timers and the User Device Defined Traps are checked separately in bit 9.

Note: Reading this register clears all the SMI status bits. Note that bits 9, 1, and 0 have another level (second) of status reporting.

A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 00h. If the value of the register must be read without

clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.

Offset 04h-05h

Second Level General Traps & Timers SMI Status Mirror Register (RO)

Reset Value = 0000h

15:6

Reserved (Read Only)

PCI Function Trap (Read Only): SMI was caused by a trapped configuration cycle (listed below)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

Trapped access to F0 PCI header registers other than F0 Index 40h-43h; SMI generation enabling is at F0 Index 41h[0].

Trapped access to F1 PCI header registers; SMI generation enabling is at F0 Index 41h[3].

Trapped access to F2 PCI header registers; SMI generation enabling is at F0 Index 41h[6].

Trapped access to F3 PCI header registers; SMI generation enabling is at F0 Index 42h[0].

Trapped access to F4 PCI header registers; SMI generation enabling is at F0 Index 42h[1].

SMI Source is Trapped Access to User Defined Device 3 (Read Only): SMI was caused by a trapped I/O or memory

access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[6].

SMI Source is Trapped Access to User Defined Device 2 (Read Only): SMI was caused by a trapped I/O or memory

access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[5].

SMI Source is Trapped Access to User Defined Device 1 (Read Only): SMI was caused by a trapped I/O or memory

access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[4].

SMI Source is Expired General Purpose Timer 2 (Read Only): SMI was caused by the expiration of General

Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 83h[1].

SMI Source is Expired General Purpose Timer 1 (Read Only): SMI was caused by the expiration of General

Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 83h[0].

Note: Reading this register does not clear the status bits. See F1BAR+Memory Offset 06h.

Offset 06h-07h

Second Level General Traps & Timers SMI Status Register (RC)

Reset Value = 0000h

15:6

Reserved (Read to Clear)

Table 5-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 182 Page - Advanced Micro Devices

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