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CS5530A Datasheet(PDF) 147 Page - Advanced Micro Devices

Part # CS5530A
Description  AMD Geode CS5530A Companion Device
PDF  259 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

CS5530A Datasheet(HTML) 147 Page - Advanced Micro Devices

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AMD Geode™ CS5530A Companion Device Data Book
147
Register Summary
Revision 1.1
Table 5-3. Function 1: PCI Header Registers for SMI Status and ACPI Timer Summary
F1 Index
Width
(Bits)
Type
Name
Reset Value
Reference
(Table 5-16)
00h-01h
16
RO
Vendor Identification Register
1078h
Page 180
02h-03h
16
RO
Device Identification Register
0101h
Page 180
04h-05h
16
R/W
PCI Command Register
0000h
Page 180
06h-07h
16
RO
PCI Status Register
0280h
Page 180
08h
8
RO
Device Revision ID Register
00h
Page 180
09h-0Bh
24
RO
PCI Class Code Register
068000h
Page 180
0Ch
8
RO
PCI Cache Line Size Register
00h
Page 180
0Dh
8
RO
PCI Latency Timer Register
00h
Page 180
0Eh
8
RO
PCI Header Type Register
00h
Page 180
0Fh
8
RO
PCI BIST Register
00h
Page 180
10h-13h
32
R/W
Base Address Register (F1BAR): Sets base address for
memory mapped SMI status and ACPI timer support regis-
ters (summarized in Table 4-4).
00000000h
Page 180
14h-3Fh
--
--
Reserved
00h
Page 180
40h-FFh
Reserved
xxh
Page 180
Table 5-4. F1BAR: SMI Status and ACPI Timer Registers Summary
F1BAR+
Memory
Offset
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-17)
00h-01h
16
RO
Top SMI Status Mirror Register
0000h
Page 181
02h-03h
16
RC
Top SMI Status Register
0000h
Page 181
04h-05h
16
RO
Second Level General Traps & Timers Status Mirror
0000h
Page 182
06h-07h
16
RC
Second Level General Traps & Timers Status Register
0000h
Page 182
08h-09h
16
Read to
Enable
SMI Speedup Disable Register
0000h
Page 183
0Ah-1Bh
--
--
Reserved
xxh
Page 183
1Ch-1Fh
32
RO
ACPI Timer Count
Note: The ACPI Timer Count Register is accessible through
I/O Port 121Ch.
00FFFFFCh
Page 183
20h-4Fh
--
--
Reserved
xxh
Page 183
50h-FFh
Note: The registers located at F1BAR+Memory Offset 50h-FFh can also be accessed at F0 Index 50h-FFh. The pre-
ferred method is to program these registers through the F0 Register Space. Refer to Table 5-2 "Function 0: PCI
Header and Bridge Configuration Registers Summary" on page 145 for summary information.



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