DP83952 datasheet(17/90 Pages) NSC

17 / 90 page

50 Functional Description

The IEEE 8023 repeater specification details a number of

functions a repeater system must perform These require-

ments allied with a need for the implementation to be multi-

port strongly favors the choice of a modular design style In

such a design functionality is split between those tasks

common to all data channels and those exclusive to each

individual channel The RIC II follows this approach certain

functional blocks are replicated for each network attach-

ment (also known as a repeater port) and others are

shared

The following sections provide an overview of the RIC II

architecture First RIC II feature enhancements from the

RIC is discussed Then the RIC II functional blocks are de-

scribed

51 SUMMARY OF DP83952 RIC II FEATURE

ENHANCEMENTS FROM DP83950B RIC

1 Pin Compatibility The DP83952VUL RIC II is fully pin

compatible with the DP83950BVQB RIC device in the

160-pin Plastic Quad Flat Pack (PQFP) package

2 Addition of network security The DP83952 RIC II fea-

tures significant per port security capability As a single

chip repeater RIC II provides security using 58 internal

CAM (Content Addressable Memory) locations for all 13

ports

Unauthorized nodes can be restricted from intruding and

or eavesdropping into the network by preventing them

from having access to valid packet data The RIC II uti-

lizes internal CAMs to storecompare addresses of valid

nodes Complete security operation of RIC II is explained

later in this datasheet

3 Two dedicated CAM locations per port and 32 shareable

CAM entries are provided to store Ethernet addresses

Both the port and the shareable CAM locations (48 bits

wide) are on-chip

4 Faster processor access for efficient data gathering

5 Addition of thirteen 8-bit wide counters for collecting

more statistics

52 OVERVIEW OF RIC II FUNCTIONS

SEGMENT SPECIFIC BLOCK NETWORK PORT

As shown in the Block Diagram the segment specific blocks

consist of

1 One or more physical layer interfaces

2 A logic block required for performing repeater operations

upon that particular segment This is known as the ‘‘port’’

logic since it is the access ‘‘port’’ the segment has to the

rest of the network

This function is repeated 13 times in the RIC II (one for each

port) and is shown on the right side of the Block Diagram

Figure 4-1

The physical layer interface depends upon the port Port 1

has an AUI compliant interface for use with AUI compatible

transceiver boxes and cable Ports 2 to 13 may be config-

ured for use with one of two interfaces twisted pair or an

external transceiver The former utilizes the RIC II’s on-chip

10BASE-T transceivers the latter allows connection to ex-

ternal transceivers When using the external transceiver

mode the interface is AUI compatible Although AUI com-

patible transceivers are supported when an interface cable

is used external transceivers should always be used for the

repeater system

Inside the port logic there are 4 distinct functions

1 The port state machine ‘‘PSM’’ is required to perform

data and collision repetition as described by the repeater

specification for example it determines whether this port

should be receiving from or transmitting to its network

segment

2 The port partition logic implements the segment partition-

ing algorithm This algorithm is defined by the IEEE speci-

fication and is used to protect the network from malfunc-

tioning segments

3 The port status register reflects the current status of the

port It may be accessed by a system processor to obtain

this status or to perform certain port configuration opera-

tions such as port disable

4 The Port Security Configuration Logic determines if the

packet data will be transmittedreceived intact or as

pseudo random data Two dedicated CAM locations per

port are available for learningstoringcomparing port

source addresses

SHARED FUNCTIONAL BLOCKS REPEATER CORE

LOGIC

The shared functional blocks consists of the Repeater Main

State Machine (MSM) Timers a 32-bit Elasticity Buffer PLL

Decoder Receive and Transmit Multiplexors and Security

Logic with 32 shareable CAM locations These blocks per-

form the majority of the operations needed to fulfill the re-

quirements of the IEEE repeater specification

When a packet is received by a port it is sent via the Re-

ceive Multiplexor to the PLL Decoder Notification of the

data and collision status is sent to the main state machine

via the receive multiplexor and collision activity status sig-

nals This enables the main state machine to determine the

source of the data to be repeated and the type of data to be

transmitted either data or jam pattern

When a collision occurs in accordance with IEEE repeater

specifications the transmit data will be a preamblejam pat-

tern consisting of a 1010

bit pattern Whenever a colli-

sion occurs (during the preamble the address field the

‘‘type field’’ or the data field) the RIC II switches to the jam

pattern immediately

When RIC II is configured in the ‘‘non-secure’’ mode the

valid received data field is transmitted to all other ports (ex-

cluding the port with the received packet)

When RIC II is configured in the ‘‘secure’’ mode the source

and destination addresses within each packet are first

checked Based on this comparison and the port configura-

tion either

1 a pseudo random bit pattern during the data field (of the

packet) is transmitted to the particular port Or

2 the received data is transmitted intact

The data remains intact on the Inter-RIC bus so other cas-

caded repeaters could compare the destination address

with their local CAMs On a valid source address mismatch

RIC II shall switch to random pattern both on the local trans-

mitting ports and the Inter-RIC bus

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