DP83952 datasheet(39/90 Pages) NSC

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50 Functional Description (Continued)

PROCESSOR ACCESS CYCLES

Access to the RIC II’s on-chip registers is made via its proc-

essor interface This utilizes conventional non-multiplexed

address (5-bit) and data (8-bit) busses The data bus is also

used to provide data and address information to off-chip

display latches during display update cycles While perform-

ing these cycles the RIC II behaves as a master of its data

bus Consequently a TRI-STATE bi-directional bus trans-

ceiver eg

74LS245 must be placed between the RIC II

and any processor bus

RIC II provides the following scheme to facilitate faster reg-

ister accesses Lower Event Information Register (Page 1H

Address 1FH) has Disable LED Update bit DLU which

when it is set then RIC II stops the LED updates This caus-

es the data bus to be no longer shared and therefore RIC II

is always in a slave access mode In this mode the maxi-

mum readwrite cycle time is reduced to approximately

400 ns

The processor requests a register access by asserting the

read ‘‘RD’’ or write ‘‘WR’’ input strobes The RIC II responds

by finishing any current display update cycle and asserts the

TRI-STATE buffer enable signal ‘‘BUFEN’’ If the processor

cycle is a write cycle then the RIC II’s data buffers are dis-

abled to prevent contention In order to interface to the

RIC II in a processor controlled system it is likely a PAL

device will be used to perform the following operations

1 locate the RIC II in the processor’s memory map (address

decode)

2 generate the RIC II’s read and write strobes

3 control the direction signal for the 74LS245

An example of the processor and display interfaces is

shown in

Figure 5-12

INTERRUPT HANDLING

The DP83952 RIC II offers an alternate method for a faster

access to determine the source of the Event Logging Inter-

rupt (ELI) then the DP83950 RIC

For an event logging interrupt due to flag found

the

DP83950 RIC

requires the following scheme

1 Read the Page Select Register (Address 10H) to locate

the source of Event Logging Interrupt

2 Read all the Port Event Recording Registers (Page 1H

Address 11H to 1DH) to find the port and the event re-

sponsible for Event Logging Interrupt

DP83952 RIC II

allows the following alternate scheme for a

faster access

1 Read Page Select Register (Address 10H) to locate the

source of Event Logging Interrupt

2 Read the Event Information Registers (Page 1H address-

es 1EH and 1FH) to locate the port responsible for inter-

rupt

3 Read the Event Recording register of that port to find

which specific event caused the Event Logging Interrupt

60 Hub Management Support

The RIC II provides information regarding the status of its

ports and the packets it is repeating This data is available in

three forms

1 Counted EventsNetwork events accumulated into the

RIC II’s 16-bit Event Counter Registers

2 Recorded EventsNetwork events that set bits in the

Event Record Registers

3 Hub Management Status packetsThis is information

sent over the Management Bus in a serial function to be

decoded by an Ethernet Controller board

The counted and recorded event information is available

through the processor interface This data is port specific

and may be used to generate interrupts via the Event Log-

ging Interrupt ‘‘ELI’’ pin Since the information is specific to

each port each repeater port has its own event record reg-

ister and event counter The counters and event record reg-

isters have user definable masks which enable them to be

configured to count and record a variety of events The

counters and record registers are designed to be used to-

gether so that detailed information ie a count value can

be held on-chip for a specific network condition More gen-

eral information ie the occurrence of certain types of

events may be retained in on-chip latches Thus the user

can configure the counters to increment upon a rapidly oc-

curring event (most likely to be used to count collisions)

and the record registers may log the occurrence of less

frequent error conditions such as jabber protect packets

61 EVENT COUNTING FUNCTION

The counters may increment upon the occurrence of one of

the categories of event as described below

Potential sources for Counter increment

Jabber Protection (JAB)

The port counter increments if

the length of a received packet from its associated port

causes the repeater state machine to enter the jabber pro-

tect state

Elasticity Buffer Error (ELBER)

The port counter incre-

ments if a Elasticity Buffer underflow or overflow occurs dur-

ing packet reception The flag is held inactive if a collision

occurs during packet reception or if a phase lock error de-

scribed below has already occurred during the repetition of

the packet

Phase Lock Error (PLER)

A phase lock error is caused if

the phase lock loop decoder looses lock during packet re-

ception Phase lock onto the received data stream may or

may not be recovered later in the packet and data errors

may have occurred This flag is held inactive if a collision

occurs

Non-SFD Packet (NSFD)

If a packet is received and the

start of frame delimiter is not found the port counter will

increment Counting is inhibited if the packet suffers a colli-

sion

Out of Window Collision (OWC)

The out of window colli-

sion flag for a port goes active when a collision is experi-

enced outside of the network slot time

Transmit Collision (TXCOL)

The transmit collision flag for

a port is enabled when a transmit collision is experienced by

the repeater Each port experiencing a collision under these

conditions is said to have suffered a transmit collision

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