DP83952 datasheet(14/90 Pages) NSC

14 / 90 page

30 Pin Description (Continued)

Pin Name

Driver

Description

Type

MANAGEMENT BUS PINS

MRXC

O Z

ANAGEMENT RECEIVE CLOCK When asserted this signal provides a clock signal for the

MRXD serial data stream The MRXD signal is changed on the falling edge of this clock The

signal is asserted when a RIC II is receiving data from one of its network segments Otherwise

the signal is inactive

MCRS

B Z

ANAGEMENT CARRIER SENSE When asserted this signal provides an activity framing

enable for the serial data stream The signal is asserted when a RIC II is receiving data from one

of its network segments Otherwise the signal is an input

MRXD

O Z

ANAGEMENT RECEIVE DATA When asserted this signal provides a serial data stream in

NRZ format The data stream is made up of the data packet and RIC II status information The

signal is asserted when a RIC II is receiving data from one of its network segments Otherwise

the signal is inactive

MEN

ANAGEMENT BUS OUTPUT ENABLE This output acts as an active high enable for an

external bus transceiver (if required) for the MRXC MCRS and MRXD signals When high the

bus transceiver should be transmitting on to the bus

PCOMP

ACKET COMPRESS This input is used to activate the RIC II’s packet compress logic A low

level on this signal when MCRS is active will cause that packet to be compressed If PCOMP is

tied low all packets are compressed if PCOMP is tied high packet compression is inhibited

POWER AND GROUND PINS

VCC

Positive Supply

GND

Negative Supply

EXTERNAL DECODER PINS

RXM

ECEIVE DATA MANCHESTER FORMAT This output makes the data in Manchester format

received by port N available for test purposes If not used for testing this pin should be left open

TT e TT

L compatible B e Bi-directional C e CMOS compatible OD e Open Drain I e Input O e Output

DP83952 Datasheet(PDF) 14 Page - National Semiconductor (TI)

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