DP83952 datasheet(59/90 Pages) NSC

59 / 90 page

80 RIC II Registers (Continued)

RIC II STATUS AND CONFIGURATION REGISTER (ADDRESS 00H)

The lower portion of this register contains real time information concerning the operation of the RIC II The upper three bits

represent the chosen configuration of the transceiver interface employed

BINV

BYPAS2

BYPAS1

APART

JAB

AREC

ACOL

resv

Bit

Symbol

Description

resv

RESERVED FOR FUTURE USE

Reads as a logic 1

ACOL

ANY COLLISIONS

0 A collision is occurring at one or more of the RIC II’s ports

1 No collisions

AREC

ANY RECEIVE

0 One of the RIC II’s ports is the current packet or collision receiver

1 No packet or collision reception within this RIC II

JAB

JABBER PROTECT

0 The RIC II has been forced into jabber protect state by one of its ports or by another port on the

Inter-RIC bus (Multi-RIC II operations)

1 No jabber protect conditions exist

APART

ANY PARTITION

0 One or more ports are partitioned

1 No ports are partitioned

BYPAS2

BYPAS1

These bits define the configuration of ports 2 to 13 ie their use if the internal 10BASE-T

transceivers or the external (AUI-like) transceiver interface

BINV

BUS INVERT

This register bit informs whether the Inter-RIC signals IRE ACTN ANYXN COLN and

Management bus signal MCRS are

0 Active high

1 Active low

DP83952 Datasheet(PDF) 59 Page - National Semiconductor (TI)

DP83952 Datasheet(HTML) 59 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL