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DP83952 Datasheet(PDF) 64 Page - National Semiconductor (TI) |
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DP83952 Datasheet(HTML) 64 Page - National Semiconductor (TI) |
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64 / 90 page  80 RIC II Registers (Continued) LOWER EVENT COUNT MASK REGISTER (PAGE 0H ADDRESS 12H) D7 D6 D5 D4 D3 D2 D1 D0 BDLNKC PARTC RECC SEC NSFDC PLERC ELBERC JABC Bit RW Symbol Description D0 RW JABC JABBER COUNT ENABLE Enables recording of Jabber Protect events D1 RW ELBERC ELASTICITY BUFFER ERROR COUNT ENABLE Enables recording of Elasticity Buffer Error events D2 RW PLERC PHASE LOCK ERROR COUNT ENABLE Enables recording of Carrier Error events D3 RW NSFDC NON-SFD COUNT ENABLE Enables recording of Non-SFD packet events D4 RW SEC SHORT EVENT COUNT ENABLE Enables recording of Short events D5 RW RECC RECEIVE COUNT ENABLE Enables recording of Packet Receive (Port N status) events that do not suffer collisions D6 RW PARTC PARTITION COUNT ENABLE Enables recording of Partition events D7 RW BDLNKC BAD LINK COUNT ENABLE Enables recording of Bad Link events UPPER EVENT COUNT MASK REGISTER (PAGE 0H ADDRESS 13H) The bits in this register effect the Upper and Lower Port Event Count Registers (ECR) on Page (3) addresses 12H to 1FH and Page (4) addresses 12H to 1DH D7 D6 D5 D4 D3 D2 D1 D0 resv resv OWCC RXCOLC TXCOLC resv FWF ROR Bit RW Symbol Description D0 RW ROR RESET ON READ This bit selects the action a read operation has upon a port’s event counter 0 No effect upon register contents 1 The counter register is reset D1 RW FWF FREEZE WHEN FULL This bit controls the freezing of the Event Count registers when the counter is full (FFFF Hex) D2 R resv RESERVED FOR FUTURE USE This bit should be written with a low logic level D3 RW TXCOLC TRANSMIT COLLISION COUNT ENABLE Enables recording of transmit collision events only D4 RW RXCOLC RECEIVE COLLISION COUNT ENABLE Enables recording of receive collision events only D5 RW OWCC OUT OF WINDOW COLLISION COUNT ENABLE Enables recording of out of window collision events only D(7 6) R resv RESERVED FOR FUTURE USE These bits should be written with a low logic level Note To count all collisions then both the TXCOLC and RXCOLC bits must be set The OWCC bit should not be set otherwise the port counter will be incremented twice when an out of collision window collision occurs The OWCC bit alone should be set if only out of window collision are to be counted 64 |
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