DP83952 datasheet(13/90 Pages) NSC

13 / 90 page

30 Pin Description (Continued)

Pin Name

Driver

Description

Type

INTER-RIC BUS PINS

ACKI

ACK

NOWLEDGE INPUT Input to the network ports’ arbitration chain

ACKO

ACK

NOWLEDGE OUTPUT Output from the network ports’ arbitration chain

IRD

B Z

NTER-RIC DATA When asserted as an output this signal provides a serial data stream in NRZ

format The signal is asserted by a RIC II when it is receiving data from one of its network

segments The default condition of this signal is to be an input In this state it may be driven by

other devices on the Inter-RIC bus

IRE

B Z

NTER-RIC ENABLE When asserted as an output this signal provides an activity framing enable

for the serial data stream The signal is asserted by a RIC II when it is receiving data from one of

its network segments The default condition of this signal is to be an input In this state it may be

driven by other devices on the Inter-RIC bus

IRC

B Z

NTER-RIC CLOCK When asserted as an output this signal provides a clock signal for the serial

data stream Data (IRD) is changed on the falling edge of the clock The signal is asserted by a

RIC II when it is receiving data from one of its network segments The default condition of this

signal is to be an input When an input IRD is sampled on the rising edge of the clock In this

state it may be driven by other devices on the Inter-RIC bus

COLN

B Z

COL

LISION ON PORT N This denotes that a collision is occurring on the port receiving the data

packet The default condition of this signal is to be an input In this state it may be driven by other

devices on the Inter-RIC bus

PKEN

ACKET ENABLE This output acts as an active high enable for an external bus transceiver

(if required) for the IRE IRC IRD and COLN signals When high the bus transceiver should be

transmitting on to the bus ie this RIC II is driving the IRD IRE IRC and COLN bus lines When

low the bus transceiver should receive from the bus

CLKIN

40 MHz CLOCKINPUT This input is used to generate the RIC II’s timing reference for the state

machines and phase lock loop decoder

ACTND

ACT

IVITY ON PORT NDRIVE This output is active when the RIC II is receiving data or collision

information from one of its network segments

ACTNS

ACT

IVITY ON PORT NSENSE This input senses when this or another RIC II in a multi-RIC II

system is receiving data or collision information

ANYXND

CTIVITY ON ANY PORT EXCLUDING PORT NDRIVE This output is active when a RIC II is

experiencing a transmit collision or multiple ports have active collisions on their network

segments

ANYXNS

CTIVITY ON ANY PORT EXCLUDING PORT NSENSE This input senses when this RIC II or

other RIC IIs in a multi-RIC II system are experiencing transmit collisions or multiple ports have

active collisions on their network segments

TT e TT

L compatible B e Bi-directional C e CMOS compatible OD e Open Drain I e Input O e Output

DP83952 Datasheet(PDF) 13 Page - National Semiconductor (TI)

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