DP83952 datasheet(40/90 Pages) NSC

40 / 90 page

60 Hub Management Support (Continued)

Receive Collision (RXCOL)

The receive collision flag for a

port goes active when the port is the receive source of net-

work activity and suffers a collision provided no other net-

work segments experience collisions then the receive colli-

sion flag for the receiving port will be set

Partition (PART)

The port counter increments when a port

becomes partitioned

Bad Link (BDLNK)

The port counter increments when a

port is configured for 10BASE-T operation has entered the

link lost state

Short Event reception (SE)

The port counter increments if

the received packet is less than 74 bits long and no collision

occurs during reception

Packet Reception (REC)

When a packet is received the

port counter increments

In order to utilize the counters the user must choose from

the above list the desired statistic for counting This counter

mask information must be written to the appropriate Event

Count Mask Register There are two of these registers the

Upper and Lower Event Count Mask registers For the exact

bit patterns of these registers please see Section 8 of the

data sheet

For example if the counters are configured to count network

collisions and the appropriate masks have been set then

whenever a collision occurs on a segment this information

is latched by the hub management support logic At the end

of repetition of the packet the collision status respective to

each port is loaded into that port’s counter This operation

is completely autonomous and requires no processor inter-

vention

Each counter is 16 bits long and may be directly read by the

processor Additionally each counter has a number of de-

codes to indicate the current value of the count There are

three decodes

low count (a value of 00FF Hex and under)

high count (a value of C000 Hex and above)

full count (a value of FFFF Hex)

The decodes from each counter are logically ‘‘ORed’’ to-

gether and may be used as interrupt sources for the ELI

interrupt pin Additionally the status of these bits may be

observed by reading the Page Select Register (PSR) (see

Section 8 for register details) In order to enable any of

these threshold interrupts the appropriate interrupt mask bit

must be written to the Management and Interrupt Configura-

tion Register see Section 8 for register details

In addition to their event masking functions the Upper

Event Counting Mask Register (UECMR) possesses two

bits which control the operation of the counters When writ-

ten to a logic one the reset on read bit ‘‘ROR’’ resets the

counter after a processor read cycle is performed If this

operation is not selected then in order to zero the counters

they must either be written with zeros by the processor or

allowed to roll over to all zeros The freeze when full bit

‘‘FWF’’ prevents counter roll over by inhibiting count up cy-

cles (these happen when chosen events occur) thus freez-

ing the particular counter at FFFF Hex

The port event counters may also be controlled by the

Counter Decrement (CDEC) pin As its name suggests a

logic low state on this pin will decrement all the counters by

a single value The pulses on CDEC are internally synchro-

nized and scheduled so as not to conflict with any ‘‘up

counting’’ activity If an up count and a down count occur

simultaneously then the down count is delayed until the up

count has completed This combination of up and down

counting capability enables the RIC II’s on-chip counters to

provide a simple rolling average or be used as extensions

of larger off-chip counters

Note

If the FWF option is enabled then the count down operation is dis-

abled from those registers which have reached FFFF Hex and conse-

quently have been frozen Thus if FWF is set and CDEC has been

employed to provide a rate indication A frozen counter indicates that

a rate has been detected which has gone out of bounds ie too fast

increment or too slow increment If the low count and high count

decodes are employed as either interrupt sources or in a polling cycle

the direction of the rate excursion may be determined

NEW HUB MANAGEMENT COUNTERS

The RIC II adds 13 more 8-bit counters then provided on the

DP83950 RIC These counters will count events specified in

the Event Count and Interrupt Mask Register 2 (ECIMR2)

such as Frame Check Sequence Frame Alignment Error

Partition Out of Window Collision This register also in-

cludes ‘‘Reset On Read’’ and ‘‘Freeze When Full’’ control

bits

It should be noted that Counter Decrement (CDEC) will not

be used with the ECMR2 Also no real time or event logging

interrupt RTI or ELI will be generated for this register

READING THE EVENT COUNTERS

The RIC II’s external data bus is eight bits wide since the

event counters are 16 bits long two processor read cycles

are required to yield the counter value In order to ensure

that the read value is correct and to allow simultaneous

event counts with processor accesses a temporary holding

upper byte of a counter causes both bytes to be latched

into the holding register Thus when the other byte of the

counter is obtained the holding register is accessed and

not the actual counter register This ensures that the upper

and lower bytes contain the value sampled at the same in-

stance in time ie when the first read cycle to that counter

occurred

There is no restriction concerning whether the upper or low-

er byte is read first However to ensure the ‘‘same instance

value’’ is obtained the reads of the upper then lower byte

(or vice versa) should be performed as consecutive reads of

the counter array Other NON-COUNTER registers may be

read in between these read cycles and also write cycles

may be performed If another counter is read or the same

byte of the original counter is read again then the holding

byte is lost

If the reset on read option is employed then the counter is

reset after the transfer to the holding register is performed

Processor read and write cycles are scheduled in such a

manner that they do not conflict with count up or count

down operations That is to say in the case of a processor

read the count value is stable when it is loaded into the

holding register In the case of a processor write the newly

written value is stable so it may be incremented or decre-

mented by any subsequent count operation During the peri-

od the MLOAD pin is low (power on reset) all counters are

DP83952 Datasheet(PDF) 40 Page - National Semiconductor (TI)

DP83952 Datasheet(HTML) 40 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL