DP83952 datasheet(32/90 Pages) NSC

32 / 90 page

50 Functional Description (Continued)

It is important to note that RIC II will learn the address of the

packet if LME is set regardless of the D0 setting of MLOAD

ie secure or non-secure mode

It is also very important to note that for proper address

learning LME and SAC should not be set together

When the repeater is in non-secure mode then the compar-

ison will not take place between the incoming address and

the learned address

When the repeater is in secure mode and the LME bit is

set then the processor readwrite access will be ignored for

the port CAM entries That is readwrite cycles are complet-

ed however unknown values are read during the learning

process Data will not be written into the CAM entries until

the end of the learning process

It may be desired not to randomize the outgoing data and

transmit the data intact when there is a valid source address

mismatch The Generate Random Pattern bit GRP in the

Global Security Register will provide the option

If GRP is set (GRPe1) and there is a source address mis-

match then RIC II will not generate random pattern the

packet will be transmitted out and the Hub Manager will be

informed about the source address mismatch

For this option to work properly

GRPeESAe1 and

EDAe0 If EDA is also set to 1 then the packet will be

randomized on ports with valid DA mismatches and this

functionality will not work

TABLE 5-1 Pin Definitions for Options in the Mode Load Operation

Programming

Effect When

Function

Name

Function

Bit is 0

Bit is 1

SCRTY

Security

Non-Security

This bit configures RIC II security feature options

Mode

When D0 e 0 LME SME ESA EDA bits in the Port Security

Configuration Register (PSCR) are set globally

When D0 e1 security can still be done but now the user

needs to set the above bits in the PSCR register

TW2

5 Bits

3 Bits

This allows the user to select one of two values for the

repeater specification TW2 time The lower limit (3 bits) meets

the IEEE specification The upper limit (5 bits) is not

specification compliant but may provide users with higher

network throughput by avoiding spurious network activity gaps

when using coaxial (10BASE2 10BASE5) network segments

CCLIM

The partition specification requires a port to be partitioned

after a certain number of consecutive collisions The RIC II

has two values available to allow users to customize the

partitioning algorithm to their environment Please refer to the

Partition State Machine in data sheet Section 73

LPPART

Selected

Not Selected

The RIC II may be configured to partition a port if the segment

transceiver does not loopback data to the port when the port

is transmitting to it as described in the Partition State

Machine

OWCE

Selected

Not Selected

This configuration bit allows the on-chip partition algorithm to

include out of window collisions into the collisions it monitors

as described in the Partition State Machine

TXONLY

Selected

Not Selected

This configuration bit allows the on-chip partition algorithm to

restrict segment reconnection as described in the Partition

State Machine

DPART

Selected

Not Selected

The Partition state machines for all ports may be disabled by

writing a logic zero to this bit during the mode load operation

MINMAX

Minimum

Maximum Mode

The operation of the display update block is controlled by the

Mode

value of this configuration bit as described in the Display

Update Cycles section

DP83952 Datasheet(PDF) 32 Page - National Semiconductor (TI)

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