DP83952 datasheet(23/90 Pages) NSC

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50 Functional Description (Continued)

METHODS OF RIC II CASCADING

In order to build multi-RIC II repeaters

PORT N and

PORT M identification must be performed across all the RIC

IIs in the system Inside each RIC II the PSMs are arranged

in a logical arbitration chain where port 1 is the highest and

port 13 the lowest The top of the chain the input to port 1 is

accessible to the user via the RIC II’s ACKI input pin The

output from the bottom of the chain becomes the ACKO

output pin In a single RIC II system

PORT N is defined as

the highest port in the arbitration chain with receive or colli-

sion activity

Port N identification is performed when the re-

peater is in the

IDLE state PORT M is defined as the high-

est port in the chain with a collision when the repeater

leaves the

TRANSMIT COLLISION state In order for the

arbitration chain to function all that needs to be done is to

tie the ACKI signal to a logic high state In multi-RIC II sys-

tems there are two methods to propagate the arbitration

chain between RIC IIs

The first and most straightforward is to extend the arbitra-

tion chain by daisy chaining the ACKI-ACKO signals be-

tween RIC IIs In this approach one RIC II is placed at the

top of the chain (its ACKI input is tied high) then the ACKO

signal from this RIC II is sent to the ACKI input of the next

RIC II and so on This arrangement is simple to implement

but it places some topological restrictions upon the repeater

system In particular if the repeater is constructed using a

backplane with removable printed circuit boards (These

boards contain the RIC IIs and their associated compo-

nents) If one of the boards is removed then the ACKI-

ACKO chain will be broken and the repeater will not operate

correctly

The second method of

PORT N or M identification avoids

this problem This second technique relies on an external

parallel arbiter which monitors all of the RIC IIs’ ACKO sig-

nals and responds to the RIC II with the highest priority In

this scheme each RIC II is assigned with a priority level One

method of doing this is to assign a priority number which

reflects the position of a RIC II board on the repeater back-

plane ie its slot number When a RIC II experiences re-

ceive activity and the repeater system is in the

IDLE state

the RIC II board will assert ACKO External arbitration logic

drives the identification number onto an arbitration bus and

the RIC II containing

PORT N will be identified An identical

procedure is used in the

TRANSMIT COLLISION state to

identify

PORT M Parallel arbitration is not subject to the

problems caused by missing boards ie empty slots in the

backplane The logic associated with asserting this arbitra-

tion vector in the various packet repetition scenarios could

be implemented in PAL

or GAL

type devices

Both of the above methods employ the same signals ACKI

ACKO and ACTN to perform

PORT N or M arbitration

The Inter-RIC bus allows multi-RIC II operations to be per-

formed in exactly the same manner as if there is only a

single RIC II in the system The simplest way to describe the

operation of Inter-RIC bus is to see how it is used in a num-

ber of common packet repetition scenarios Throughout this

description the RIC IIs are presumed to be operating in ex-

ternal transceiver mode This is advantageous for the expla-

nation since the receive transmit and collision signals from

each network segment are observable In internal transceiv-

er mode this is not the case since the collision signal for the

non-AUI ports is derived by the transceivers inside the

RIC II

54 EXAMPLES OF PACKET REPETITION SCENARIOS

The operation of RIC II is described by the following exam-

ples of packet repetition scenarios

DATA REPETITION OVERVIEW

When a packet is received at one port RIC II checks the

source and destination addresses of the packet The port

configuration causes either a pseudo random bit sequence

or the received packet to be transmitted to different ports

If there is a destination address mismatch (secure mode)

then the RIC II will generate a random pattern on the first bit

of the data field on the corresponding transmitting port The

data remains intact on the Inter-RIC bus so other cascaded

repeaters could compare the destination address with their

local CAMs

On a valid source address mismatch (secure mode) RIC II

shall switch to random pattern both on the local transmitting

ports and the Inter-RIC bus

COLLISION SCENARIOS OVERVIEW

The RIC II will adhere to all collision scenarios When a

collision occurs RIC II will switch from a random pattern to a

jam pattern to comply with IEEE repeater specifications

If collision occurs during the preamble then jam pattern is

transmitted out by the repeater’s ports

In the case of a collision during the address field the ‘‘type

field’’ or the ‘‘data field’’ RIC II switches to the jam pattern

immediately

FIFO CONDITION OVERVIEW

Elasticity buffer error (ELBER) or FIFO overflow burst is an-

other condition that could take place anytime during the

packet transmission The sequence of events for FIFO burst

is the same as those for collision

DATA REPETITION PROCESS

The first task to be performed is

PORT N identification This

is an arbitration process performed by the Port State Ma-

chines in the system In situations where two or more ports

simultaneously receive packets the Inter-RIC bus operates

by choosing one of the active ports and forcing the others

to transmit data (real data or pseudo random data) This is

done in accordance with the IEEE specification’s allowed

exit paths from the

IDLE state ie to the SEND PREAM-

BLE PATTERN or RECEIVE COLLISION states

The packet begins with a preamble pattern derived from the

RIC II’s on-chip jampreamble generator The data received

PORT N is directed through the receive multiplexor to the

PLL decoder Once phase lock has been achieved the de-

coded data (in NRZ format) with its associated clock and

enable signals is asserted onto the IRD IRE and IRC Inter-

RIC bus lines respectively This serial data stream is re-

ceived from the bus by all RIC IIs in the repeater and direct-

ed to their Elasticity Buffers Logic circuits monitor the data

stream and look for the Start of Frame Delimiter (SFD)

When this has been detected data is loaded into the elas-

ticity buffer for later transmission This will occur when suffi-

cient preamble has been transmitted and certain internal

state machine operations have been fulfilled

Figure 5-3 shows two RIC IIs A and B daisy chained togeth-

er with RIC II A positioned at the top of the chain A packet

is received at port B1 of RIC II B and is then repeated by

the other ports in the system (non-secure mode)

Figure 5-4

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