DP83952 datasheet(12/90 Pages) NSC

12 / 90 page

30 Pin Description (Continued)

Pin Name

Driver

Description

Type

PROCESSOR BUS PINS

RA0 – RA4

EGISTER ADDRESS INPUTS These five pins are used to select a register to be read or

written The state of these inputs are ignored when the read write and mode load input strobes

are high (Even under these conditions these inputs must not be allowed to float to an undefined

logic state)

STR0

DISPLAY UPDATE STROBE 0

Maximum Display Mode

This signal controls the latching of display data for network ports 1 to

7 into the off chip display latches

Minimum Display Mode

This signal controls the latching of display data for the RIC II into the

off chip display latch

During processor access cycles (read or write is asserted) this signal is inactive (high)

STR1

DISPLAY UPDATE STROBE 1

Maximum Display Mode

This signal controls the latching of display data for network ports 8 to

13 into the off-chip display latches

Minimum Display Mode

No operation

During processor access cycles (read or write is asserted) this signal is inactive (high)

D0–D7

B Z

ATA BUS (Note 1)

Display Update Cycles

These pins become outputs providing display data and port address

information Address information only available in Maximum Display mode

Processor Access Cycles

Data input or output is performed via these pins The read write

and mode load inputs control the direction of the signals

BUFEN

BUF

FER ENABLE This output controls the TRI-STATE operation of the bus transceiver which

provides the interface between the RIC II’s data pins and the processor’s data bus (Note 2)

RDY

DATA READY STROBE The falling edge of this signal during a read cycle indicates that data is

stable and valid for sampling In write cycles the falling edge of RDY denotes that the write data

has been latched by the RIC II Therefore data must have been available and stable for this

operation to be successful

ELI

VENT LOGGING INTERRUPT A low level on the ELI output indicates the RIC II’s hub

management logic requires CPU attention The interrupt is cleared by accessing the Port Event

Recording register or Event Counter that produced it All interrupt sources may be masked

RTI

EAL TIME INTERRUPT A low level on the RTI output indicates the RIC II’s real time (packet

specific) interrupt logic requires CPU attention The interrupt is cleared by reading the Real Time

Interrupt Status register All interrupt sources may be masked

CDEC

OUNTER DECREMENT A rising edge on the CDEC input strobe decrements all of the RIC II’s

Port Event Counters by one This input is internally synchronized and if necessary the operation

of the signal is delayed if there is a simultaneous internally generated counting operation

ITE STROBE Strobe from the CPU used to write an internal register defined by the RA0 –

RA4 inputs

EAD STROBE Strobe from the CPU used to read an internal register defined by the RA0 – RA4

inputs

MLOAD

DEVICE RESET AND MODE LOAD When this input is low all of the RIC II’s state machines

counters and network ports are reset and held inactive On the rising edge of MLOAD the logic

levels present on the D0 – 7 pins and RA0 – RA4 inputs are latched into the RIC II’s configuration

registers The rising edge of MLOAD also signals the beginning of the display test operation

Note 1

The data pins remain in their display update function ie asserted as outputs unless either the read or write strobe is asserted

Note 2

The buffer enable output indicates the function of the data pins When it is high they are performing display update cycles when it is low a processor

access or mode load cycle is occurring

DP83952 Datasheet(PDF) 12 Page - National Semiconductor (TI)

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