Data Sheet

AD9530

Rev. 0 | Page 31 of 41

CONTROL REGISTER MAP DESCRIPTIONS

Table 23 through Table 61 provide detailed descriptions for each of the control register functions. The registers are listed by hexadecimal address.

Bit fields noted as live indicate that the register write takes effect immediately. Bit fields that are not noted as live only take effect after an

IO_UPDATE is issued by writing 0x01 to Register 0x00F.

SPI CONFIGURATION (REGISTER 0x000 AND REGISTER 0x001)

Table 23. Bit Descriptions for SPI_CONFIGA (Default: 0x00)

Bits

Bit Name

Settings

Description

Reset

Access

7

SOFT_RESET

Master SPI reset. Setting this self clearing bit to 1 resets the AD9530.

This bit is live.

0b

W

6

LSB_FIRST

Selects SPI LSB first mode. This bit is live.

0b

RW

0

MSB first SPI access.

1

LSB first SPI access.

5

ADDRESS_ASCEND

Selects SPI address ascend mode. This bit is live.

0b

RW

0

SPI streaming mode addresses decrement (default).

1

SPI streaming mode addresses increment.

[4:3]

SDO_ACTIVE

Selects SPI 4-pin mode, which enables the SDO pin. This bit is live.

0b

RW

0

SPI 3-pin mode. The SDIO pin is bidirectional (default).

1

SPI 4-pin mode. The SDI and SDO pins are unidirectional.

2

ADDRESS_ASCEND

Selects SPI address ascend mode. This bit is live.

0b

RW

0

SPI streaming mode addresses decrement (default).

1

SPI streaming mode addresses increment.

1

LSB_FIRST

Selects SPI LSB first mode. This bit is live.

0b

RW

0

MSB first SPI access (default).

1

LSB first SPI access.

0

SOFT_RESET

Master SPI reset. Setting this self clearing bit to 1 resets the AD9530.

This bit is live.

0b

W

Table 24. Bit Descriptions for SPI_CONFIGB (Default: 0x00)

Bits

Bit Name

Settings

Description

Reset

Access

7

SINGLE_INSTRUCTION

Single instruction mode. This bit is live.

0b

RW

0

SPI streaming mode (default).

1

SPI single instruction mode.

6

RESERVED

0

When writing to Register 0x001, this bit must be 0b.

0b

W

5

READ_BUFFER

For buffered registers, this bit controls whether the value read from

the serial port is from the actual (active) registers or the buffered copy.

0b

RW

0

Reads values currently applied to the internal logic of the device (default).

1

Reads buffered values that take effect on the next assertion of

IO_UPDATE.

[4:3]

RESERVED

00

When writing to Register 0x001, these bits must be 00b.

00b

W

2

CALIBRATE VCO

VCO calibration. Setting this self clearing bit performs a VCO

calibration, which must be performed at startup as well as any time

the VCO frequency is changed. A VCO calibration also automatically

performs a divider reset (Bit 1 in this register). This bit is live.

0b

W

1

DIVIDER_RESET

Divider reset. Writing a 1 to this self clearing register stalls the outputs,

reset all dividers, and reenable the outputs. A divider reset must be

performed any time the divider values are changed. Note that if the

divider value change results in a different VCO frequency, the

CALIBRATE VCO bit (Bit 2 in this register) must be used instead.

This bit is live.

0b

W

0

RESERVED

0

When writing to Register 0x001, this bit must be 0b.

0

W