AD9530 datasheet(32/41 Pages) AD

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AD9530

Data Sheet

Rev. 0 | Page 32 of 41

STATUS (REGISTER 0x002)

Table 25. Bit Descriptions for STATUS (Default: Varies1)

Bits

Bit Name

Settings

Description

Reset

Access

PLL_LOCKED

PLL lock detect status readback

Varies

PLL unlocked

PLL locked

SIGNAL_PRESENT

Reference signal present

Varies

Reference input signal not detected

Reference input signal detected

FEEDBACK_OK

Feedback signal valid from N divider

Varies

Feedback signal from N divider not detected

Feedback signal from N divider detected

REFERENCE_OK

Logical AND of reference input signal and feedback signal

Varies

Either the reference input clock is not detected or the feedback signal is

not detected, or neither are detected

Reference input signal and feedback signal both detected

[3:2]

RESERVED

When writing to Register 0x002, these bits must be 00b

00b

[1:0]

SLEEP

Sleep mode

00b

Normal operation (default)

Undefined

Sleep mode

1 The default value reads 0xF0 under normal operation if the PLL is locked.

CHIP TYPE (REGISTER 0x003)

Table 26. Bit Descriptions for CHIP_TYPE (Default: 0x05)

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

RESERVED

Reserved.

0x0

[3:0]

CHIP_TYPE,

Bits[3:0]

The Analog Devices unified SPI protocol reserves this read only register

location for identifying the type of device. The default value of 0x05 identifies

the AD9530 as a clock IC.

0x5

PRODUCT ID (REGISTER 0x004 AND REGISTER 0x005)

Table 27. Bit Descriptions for PRODUCT_ID[3:0] (Default: 0x3F)

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

PRODUCT_ID,

Bits[3:0]

The Analog Devices unified SPI protocol reserves this read only register

location as the lower four bits of the clock part serial ID that (along with

clock chip family. No other Analog Devices chip that adheres to the Analog

Devices unified SPI has these values for Register 0x003, Register 0x004,

and Register 0x005.

0x3

[3:0]

RESERVED

Reserved.

0xF

Table 28. Bit Descriptions for PRODUCT_ID[11:4] (Default: 0x01)

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

PRODUCT_ID,

Bits[11:4]

The Analog Devices unified SPI protocol reserves this read only register

location as the upper eight bits of the clock part serial ID that (along with

clock chip family. No other Analog Devices chip that adheres to the Analog

Devices unified SPI has these values for Register 0x003, Register 0x004,

and Register 0x005.

0x01

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