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AD9530

Data Sheet

Rev. 0 | Page 18 of 41

THEORY OF OPERATION

DETAILED FUNCTIONAL BLOCK DIAGRAM

REFB

PFD

CHARGE

PUMP

N DIVIDER

(1 TO 255)

R DIVIDER

(1 TO 255)

CONTROL

INTERFACE

(SPI)

AD9530

REFA

REFB

OUT1

OUT2

SCLK

SDO

SDIO

REF_SEL

M1 DIVIDER

÷2, ÷2.5, ÷3, ÷3.5

M2 DIVIDER

÷2, ÷2.5, ÷3, ÷3.5

LOCK

DETECTOR

5.11GHz TO 5.4GHz

D1 DIVIDER

(1 TO 255)

D2 DIVIDER

(1 TO 255)

D3 DIVIDER

(1 TO 255)

D4 DIVIDER

(1 TO 255)

OUT3

OUT4

LF_1

LF_2

LF_3

BP_CAP_1

BP_CAP_2

BP_CAP_3

M3 DIVIDER

÷2, ÷2.5, ÷3, ÷3.5

VREF

Figure 15. Detailed Functional Block Diagram

OVERVIEW

The AD9530 is a fully integrated, integer-N PLL with an ultralow

noise, internal 5.11 GHz to 5.4 GHz RTWO capable of generating

<232 fs rms, (12 kHz to 20 MHz) jitter clocking signals with a

nonideal reference. The AD9530 is tailored for 40 Gbps and

100 Gbps OTN applications with stringent converter and ASIC

clocking specifications.

The AD9530 includes an on-chip PLL, an internal RTWO, and

four output channels with integrated dividers and CML drivers.

The PLL contains a partially internal active loop filter, which

requires a small number of external components to obtain loop

bandwidths lower than 15 kHz for reference phase noise

attenuation.

The four outputs of the AD9530 feature individual dividers to

generate four separate frequencies up to 2.7 GHz.

CONFIGURATION OF THE PLL

Configuration of the PLL is accomplished by programming the

various settings for the R divider, N divider, M3 divider, charge

pump current, and a calibration of the RTWO. The combination of

these settings and the loop filter determine the PLL loop

bandwidth and stability.

Successful PLL operation and satisfactory PLL loop performance

are highly dependent on proper configuration of the internal PLL

settings and loop filter. ADIsimCLK™ is a free program that helps

the design and exploration of the capabilities and features of the

AD9530, including the design of the PLL loop filter.

Phase Frequency Detector (PFD)

The PFD takes inputs from the R divider output and the

feedback divider path to produce an output proportional to the

phase and frequency difference between them. The PFD includes

an adjustable delay element that controls the width of the anti-

backlash pulse. This pulse ensures that there is no dead zone in

the PFD transfer function and minimizes phase noise and

reference spurs.

The maximum allowable input frequency into the PFD is specified

in the PFD parameter in Table 5.

Charge Pump (CP)

The CP is controlled by the PFD. The PFD monitors the phase

and frequency relationship between its two inputs and causes

the CP to pump up or pump down to charge or discharge, respec-

tively, the integrating node, which is part of the loop filter. The

integrated and filtered CP current is transformed into a voltage

that drives the tuning node of the RTWO to move the RTWO

frequency up or down. The CP current is programmable in 52 steps,

where each step corresponds to a current increase of 50 µA.

Calculate the CP current (ICP) by

ICP (µA) = 50 × (1 + x)

where x is the value written to Register 0x025, Bits[5:0].

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