AD9530 datasheet(37/41 Pages) AD

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Data Sheet

AD9530

Rev. 0 | Page 37 of 41

Bits

Bit Name

Settings

Description

Default

Access

OUT4_LDO_EN

Output 4 enable LDO.

Disabled.

Enabled (default).

OUT4_EN

Output 4 enable.

Disabled (default).

Enabled.

OUT4_DIVIDER_RESET

Setting this (self clearing) bit resets the Output 4 divider. This bit is

live, meaning IO_UPDATE is not needed for it to take effect.

VCO POWER (REGISTER 0x01C)

Table 47. Bit Descriptions for VCO_POWER (Default: 0x01)

Bits

Bit Name

Settings

Description

Default

Access

[7:2]

RESERVED

000000b

When writing to Register 0x01C, these bits must be 00b

000000b

VCO_LDO_WAIT_OVERRIDE

VCO LDO wait state override

Wait 2 sec on startup for VCO LDO stability (default)

Do not wait for VCO LDO stability

VCO_POWER

VCO power mode

Low power mode

High power mode (lower jitter) (default)

PLL LOCK DETECT CONTROL (REGISTER 0x01D)

Table 48. Bit Descriptions for PLL_LOCKDET_CONTROL (Default: 0x0C)

Bits

Bit Name

Settings

Description

Default

Access

[7:5]

RESERVED

000b

When writing to Register 0x01D, these bits must be 000b.

000b

PLL_LOCK_DET_START

PLL lock detect start measurement. This live bit enables the

lock detector.

PLL lock detector disabled (default).

PLL lock detector enabled.

[3:1]

PLL_LOCK_DET_ERR_

THRESHOLD, Bits[2:0]

000b to

111b

PLL lock detect frequency error threshold (ppb is parts per

billion and ppm is parts per million).The frequency accuracy of

the lock detector is ±25% of the lock detect setting. For example,

for the 15 ppb setting, the actual accuracy of the lock detector

is 11 ppb to 19 ppb.

010b

000b

Threshold: ±15 ppb. Update interval: 670 ms.

001b

Threshold: ±60 ppb. Update interval: 170 ms.

010b

Threshold: ±238 ppb. Update interval: 42 ms (default).

011b

Threshold: ±954 ppb. Update interval: 10 ms.

100b

Threshold: ±3.8 ppm. Update interval: 2.6 ms.

101b

Threshold: ±15 ppm. Update interval: 660 µs.

110b

Threshold: ±61 ppm. Update interval: 160 µs.

111b

Threshold: ±244 ppm. Update interval: 41 µs.

PLL_LOCK_DET_RESET

PLL lock detect disable.

PLL lock detector enabled (default).

PLL lock detector disabled.

PLL LOCK DETECT READBACK (REGISTER 0x01E AND REGISTER 0x01F)

Table 49. Bit Descriptions for PLL_LOCKDET_READBACK1 (Read Only; No Default Value)

Bits

Bit Name

Settings

Description

Default

Access

[7:0]

PLL_LOCK_DET_ERROR,

Bits[7:0]

PLL lock detect error, Bits[7:0]. This read only register, along with Bits[1:0]

of Register 0x01F, form a 10-bit number that allows the user to read back

the magnitude of the frequency error at the phase frequency detector.

Bit 3 in Register 0x01F indicates whether the phase error measurement is

in parts per million (ppm) or parts per billion (ppb).

Varies

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