AD9530 datasheet(39/41 Pages) AD

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Data Sheet

AD9530

Rev. 0 | Page 39 of 41

M3 DIVIDER (REGISTER 0x022)

Table 53. Bit Descriptions for M3_DIVIDER (Default: 0x02)

Bits

Bit Name

Settings

Description

Default

Access

[7:4]

RESERVED

0x0

When writing to Register 0x01F, these bits must be 0x0.

0x0

[3:2]

M3_DIVIDER

These bits control the divide ratio for the M3 divider.

00b

Divide by 2 (default).

Divide by 2.5.

Divide by 3.

Divide by 3.5.

M3_EN

M3 divider enable.

Disabled.

Enabled (default).

M3_DIVIDER_RESET

Setting this (self clearing) bit resets the M3 divider. This bit is live,

meaning IO_UPDATE is not needed for it to take effect.

N DIVIDER (REGISTER 0x023)

Table 54. Bit Descriptions for N_DIVIDER (Default: 0x0A)

Bits

Bit Name

Settings

Description

Default

Access

[7:0]

N_DIVIDER

0x01 to

0xFF

PLL feedback divider. These bits control the divide ratio of the PLL

feedback divider. The divide ratio ranges from ÷1 (by writing 0x01) to

÷255 by writing 0xFF. Writing 0x00 disables the divider.

0x0A

N DIVIDER CONTROL (REGISTER 0x024)

Table 55. Bit Descriptions for N_DIVIDER_CTRL (Default:0x00)

Bits

Bit Name

Settings

Description

Default

Access

[7:1]

RESERVED

0000000b

When writing to Register 0x024, these bits must be 0x00.

0000000b

N_DIVIDER_RESET

Setting this (self clearing) bit resets the N divider (also called

the feedback divider). This bit is live, meaning IO_UPDATE is not

needed for it to take effect.

CHARGE PUMP (REGISTER 0x025)

Table 56. Bit Descriptions for CHARGE_PUMP (Default: 0x07)

Bits

Bit Name

Settings

Description

Default

Access

[7:6]

RESERVED

00b

When writing to Register 0x025, these bits must be 0x0.

00b

[5:0]

CP_CURRENT

Charge pump current. Charge pump current, ICP, is equal to: (1 +

CP_CURRENT) × 50 µA. The allowable range is 50 µA to 2.6 mA. Higher

0x07

000000b

50 µA.

000001b

100 µA.

…

000111b

400 µA (default).

…

110010b

2.55 mA.

110011

2.6 mA (maximum).

PHASE FREQUENCY DECTECTOR (REGISTER 0x026)

Table 57. Bit Descriptions for PHASE_FREQUENCY_DETECTOR (Default: 0x01)

Bits

Bit Name

Settings

Description

Default

Access

[7:2]

RESERVED

000000b

When writing to Register 0x026, these bits must be 0x00.

000000b

PFD_EN_ANTIBACKLASH

PFD antibacklash enable.

Normal antibacklash pulse width (default).

Elongated antibacklash pulse width.

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