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AD9530 Datasheet(PDF) 35 Page - Analog Devices

Part # AD9530
Description  4 CML Output, Low Jitter Clock Generator
PDF  41 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9530 Datasheet(HTML) 35 Page - Analog Devices

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Data Sheet
AD9530
Rev. 0 | Page 35 of 41
OUT1 DIVIDER (REGISTER 0x014)
Table 39. Bit Descriptions for OUT1_DIVIDER (Default: 0x01)
Bits
Bit Name
Settings
Description
Default
Access
[7:0]
OUT1_DIVIDER,
Bits[7:0]
0x00 to
0xFF
Output 1 divider. These bits control the divide ratio of the output divider.
Divide ratio goes from ÷1 (by writing 0x01) to ÷255 (by writing 0xFF).
Writing 0x00 disables the divider.
0x01
RW
OUT1 DRIVER CONTROL REGISTER (REGISTER 0x015)
Table 40. Bit Descriptions for OUT1_DRIVER_CONTROL (Default: 0x24)
Bits
Bit Name
Settings
Description
Default
Access
[7:6]
RESERVED
00
When writing to Register 0x015, these bits must be 00b.
00b
W
[5:4]
OUT1_AMP_TRIM
Output 1 amplitude voltage trim.
10b
RW
00
0.8 V.
01
0.9 V.
10
1.0 V (default).
11
1.1 V.
3
OUT1_TERM_EN
Output 1 on-chip termination.
0b
RW
0
Disabled (default).
1
Enabled.
2
OUT1_LDO_EN
Output 1 enable LDO.
1b
RW
0
Disabled.
1
Enabled (default).
1
OUT1_EN
Output 1 enable.
0b
RW
0
Disabled (default).
1
Enabled.
0
OUT1_DIVIDER_RESET
Setting this (self clearing) bit resets the Output 1 divider. This bit is
live, meaning IO_UPDATE is not needed for it to take effect.
0b
W
OUT2 DIVIDER (REGISTER 0x016)
Table 41. Bit Descriptions for OUT2_DIVIDER (Default: 0x01)
Bits
Bit Name
Settings
Description
Default
Access
[7:0]
OUT2_DIVIDER,
Bits[7:0]
0x00 to
0xFF
Output 2 divider. These bits control the divide ratio of the output divider.
Divide ratio goes from ÷1 (by writing 0x01) to ÷255 (by writing 0xFF).
Writing 0x00 disables the divider.
0x01
RW
OUT2 DRIVER CONTROL (REGISTER 0x017)
Table 42. Bit Descriptions for OUT2_DRIVER_CONTROL (Default: 0x24)
Bits
Bit Name
Settings
Description
Default
Access
[7:6]
RESERVED
00
When writing to Register 0x017, these bits must be 00b.
00
W
[5:4]
OUT2_AMP_TRIM
Output 2 amplitude voltage trim.
10b
RW
00
0.8 V.
01
0.9 V.
10
1.0 V (default).
11
1.1 V.
3
OUT2_TERM_EN
Output 2 on-chip termination.
0b
RW
0
Disabled (default).
1
Enabled.
2
OUT2_LDO_EN
Output 2 enable LDO.
1b
RW
0
Disabled.
1
Enabled (default).
1
OUT2_EN
Output 2 enable.
0b
RW
0
Disabled (default).
1
Enabled.



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