AD9530 datasheet(23/41 Pages) AD

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Data Sheet

AD9530

Rev. 0 | Page 23 of 41

SERIAL CONTROL PORT

The AD9530 serial control port is a flexible, synchronous serial

communications port that provides a convenient interface to

many industry-standard microcontrollers and microprocessors.

The serial control port allows read/write access to the AD9530

The AD9530 uses the Analog Devices, Inc., unified SPI protocol.

The unified SPI protocol guarantees that all new Analog Devices

products using the unified protocol have consistent serial port

characteristics. The SPI port configuration is programmable via

rather than in the register map.

SPI SERIAL PORT OPERATION

Pin Descriptions

The SCLK (serial clock) pin serves as the serial shift clock. This

pin is an input. SCLK synchronizes serial control port read and

write operations. The rising edge SCLK registers write data bits,

and the falling edge registers read data bits. The SCLK pin

supports a maximum clock rate of 40 MHz.

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB-first

and LSB-first data formats. Both the hardware configuration

and data format features are programmable. The 3-wire mode

uses the SDIO (serial data input/output) pin for transferring

data in both directions. The 4-wire mode uses the SDIO pin

for transferring data to the AD9530, and the SDO pin for

transferring data from the AD9530.

The CS (chip select) pin is an active low control that gates read

and write operations. Assertion (active low) of the CS pin initiates a

write or read operation to theAD9530 SPI port. Any number of

data bytes can be transferred in a continuous stream. The register

address is automatically incremented or decremented based on the

setting of the address ascension bit (Register 0x0000). CS must be

deasserted at the end of the last byte transferred, thereby ending

the stream mode. This pin is internally connected to a 10 kΩ pull-

up resistor. When CS is high, the SDIO and SDO pins go into a

high impedance state.

Implementation Specific Details

A detailed description of the unified SPI protocol can be found

at www.analog.com/ADISPI, which covers items such as timing,

command format, and addressing.

The following product specific items are defined in the unified

SPI protocol:

•

Analog Devices unified SPI protocol Revision: 1.0.

•

Chip type: 0x05 (0x05 indicates a clock chip).

•

Product ID: 10011b (in this case) uniquely identifies the

device as AD9530. No other Analog Devices clock IC

supporting unified SPI has this identifier.

•

Physical layer: 3-wire and 4-wire supported and 2.5 V

operation supported.

•

Optional single-byte instruction mode: not supported.

•

Data link: not used.

•

Control: not used.

Communication Cycle—Instruction Plus Data

The unified SPI protocol consists of a two part communication

cycle. The first part is a 16-bit instruction word that is coincident

with the first 16 SCLK rising edges and a payload. The instruction

word provides the AD9530 serial control port with information

regarding the payload. The instruction word includes the R/W bit

that indicates the direction of the payload transfer (that is, a

read or write operation). The instruction word also indicates

the starting register address of the first payload byte.

Write

If the instruction word indicates a write operation, the payload

is written into the serial control port buffer of the AD9530. Data

bits are registered on the rising edge of SCLK. Generally, it does

not matter what data is written to blank registers; however, it is

customary to use 0s. Note that there may be reserved registers

with default values not equal to 0x00; however, every effort was

made to avoid this.

Most of the serial port registers are buffered (see the Buffered/

Active Registers section for details on the difference between

buffered and active registers). Therefore, data written into

buffered registers does not take effect immediately. An additional

operation is needed to transfer buffered serial control port

contents to the registers that actually control the device. This

transfer is accomplished with an IO_UPDATE operation, which

is performed in one of two ways. One method is to write a Logic 1

to Register 0x00F, Bit 0 (this bit is an autoclearing bit). The user

can change as many register bits as desired before executing an

IO_UPDATE command. The IO_UPDATE operation transfers

the buffer register contents to their active register counterparts.

AD9530 Datasheet(PDF) 23 Page - Analog Devices

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