AD9530 datasheet(19/41 Pages) AD

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Data Sheet

AD9530

Rev. 0 | Page 19 of 41

PLL Active Loop Filter

The AD9530 active loop filter consists of an internal op amp,

internal passive components, and external passive components.

Proper loop filter configuration is application dependent. An

example of a second-order loop filter is shown in Figure 16.

LF_1

VREF

OP AMP

BIAS

ACTIVE LOOP FILTER WITH DUAL PATH

LF_2

LF_3

RTWO

CIN

CMAIN

RMAIN

RA_ONCHIP

CA_OFFCHIP

GND

OFF-CHIP

COMPONENTS

VTUNE_MAIN

VTUNE_TEMP

Figure 16. External Second-Order Loop Filer Configuration

C1, C2, CA_OFFCHIP, and R2 are external components required for

proper loop filter operation. All internal loop filter components

(RMAIN, RA_ONCHIP, CMAIN) are fixed with the exception of CIN, which

has available settings of 5 pF to 192.5 pF by programming

bandwidth of the loop filter op amp. CIN is composed of a fixed

5 pF capacitor and a bank of 15 selectable 12.5 pF capacitors.

Calculate the CIN value by

CIN = 5 pF + 12.5 pF × Register 0x027, Bits[5:2]

Note that RMAIN and CMAIN in Figure 16 form a pole at

approximately 2 MHz.

Table 17 shows the typical loop filter component values and CP

settings for an 8 kHz loop bandwidth.

The maximum allowable capacitance value for the external loop

filter design is shown in Table 5. Exceeding this value may cause

various functions of the AD9530 to become unstable.

Use the ADIsimCLK design tool to design and simulate loop

filters with varying bandwidths.

PLL Reference Inputs

The AD9530 features two fully differential PLL reference inputs

that are routed through a 2:1 mux to a common R divider. The

differential reference input receiver has four internal termination/

biasing options to accommodate many input logic types. A

functional diagram of the reference input receiver is shown in

Figure 17. Table 18 details the four possible reference input

termination and common-mode settings achievable by writing

to Register 0x012, Bits[3:2] and Register 0x013, Bits[3:2]. The

input frequency specifications for the reference inputs are listed

in Table 4.

VTT BIAS

Ω

10k

Ω

10k

Ω

Figure 17. Reference Input Receiver Functional Diagram

Each REFx/REFx receiver can be disabled by setting the

associated reference enable bit to 0.

RTWO

The internal RTWO tunes from 5.11 GHz to 5.4 GHz and is

has two modes: high performance mode and low power mode.

These modes are set by Register 0x01C, Bit 0. These modes

enable optimization between the phase noise performance and

power consumption. See the Power Supply Recommendations

section for a recommended power supply configuration for

Pin 20 to Pin 23.

Table 17. Typical Loop Filter Components and ICP Settings for 8 kHz Loop Bandwidth

Reference (MHz)

R Divider

Feedback Divider (N × M3)

C1 (nF)

C2 (µF)

R2 (Ω)

CA_OFFCHIP (µF)

ICP (mA)

181.5

÷1

÷30

0.47

255

0.1

0.3

Table 18. Possible Reference Input Termination Settings

Mode Name

REFx/REFx Input Termination Select Settings

On-Chip Termination

Common-Mode Bias

DC-Coupled LVDS

100 Ω differential

High-Z

DC-Coupled, Internally Biased

01 (default)

50 Ω to GND

GND

AC-Coupled

50 Ω to 0.35 V

0.35 V

DC-Coupled High-Z

10 kΩ to GND

GND

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