AD9530 datasheet(10/41 Pages) AD

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AD9530

Data Sheet

Rev. 0 | Page 10 of 41

CLOCK OUTPUT ABSOLUTE TIME JITTER (HIGH LOOP BANDWIDTH) SPECIFICATIONS

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CML OUTPUT ABSOLUTE TIME JITTER

fs rms

REFA enabled and ac-coupled; R divider = 1; Mx divider value = 2; loop

bandwidth = 80 kHz; output divider bypassed; single-ended output

swing level = 1000 mV; no internal termination; VCO in high power

mode; reference frequency = 860 MHz; output frequency = 2.58 GHz;

integration bandwidth = 12 kHz to 20 MHz; absolute jitter value also

depends on the noise of the input clock in the 12 kHz to 80 kHz range

RESET AND REF_SEL PINS SPECIFICATIONS

Table 11.

Parameter

Min

Typ

Max

Unit

INPUT CHARACTERISTICS

Voltage

Logic 1

VDD − 0.5

VDD

Logic 0

0.5

Current

Logic 1

µA

Logic 0

µA

Capacitance

RESET TIMING

Pulse Width Low

100

RESET Inactive to Start of Register Programming

LD PIN SPECIFICATIONS

Table 12.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

1 mA output load

Output Voltage

High

VOH

VDD − 0.5

Low

VOL

0.5

SERIAL CONTROL PORT SPECIFICATIONS

Table 13.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 75 kΩ pull-up resistor

Input Voltage

Logic 1

VDD − 0.4

Logic 0

0.4

Input Current

Logic 1

µA

Logic 0

µA

Input Capacitance

SCLK (INPUT)

SCLK has an internal 75 kΩ pull-down resistor

Input Voltage

Logic 1

VDD − 0.4

Logic 0

0.4

Input Current

Logic 1

µA

Logic 0

µA

Input Capacitance

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