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AD9530 Datasheet(PDF) 24 Page - Analog Devices

Part # AD9530
Description  4 CML Output, Low Jitter Clock Generator
PDF  41 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9530 Datasheet(HTML) 24 Page - Analog Devices

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AD9530
Data Sheet
Rev. 0 | Page 24 of 41
Read
If the instruction word indicates a read operation, the next
N × 8 SCLK cycles clock out the data starting from the address
specified in the instruction word. N is the number of data bytes
read. The readback data is driven to the pin on the falling edge
and must be latched on the rising edge of SCLK. Blank registers
are not skipped over during readback.
A readback operation takes data from either the serial control
port buffer registers or the active registers, as determined by
Register 0x001, Bit 5.
SPI Instruction Word (16 Bits)
The MSB of the 16-bit instruction word is R/W, which indicates
whether the instruction is a read or a write. The next 15 bits are
the register address (A14 to A0), which indicates the starting
register address of the read/write operation (see Table 20). Note
that, because there are no registers that require more than
13 address bits, A14 and A13 are ignored and treated as zeros.
SPI MSB/LSB First Transfers
The AD9530 instruction word and payload can be MSB first or
LSB first. The default for the AD9530 is MSB first. The LSB first
mode can be set by writing a 1 to Register 0x000, Bit 6 and Bit 1.
Immediately after the LSB first bit is set, subsequent serial
control port operations are LSB first.
Address Ascension
If the address ascension bit (Register 0x000, Bit 5 and Bit 2) = 0,
the serial control port register address decrements from the
specified starting address toward Address 0x0000.
If the address ascension bit (Register 0x0000, Bit 5 and Bit 2) = 1,
the serial control port register address increments from the
starting address toward Address 0x0FF. Reserved addresses are
not skipped during multibyte input/output operations;
therefore, write the default value to a reserved register and 0s to
unmapped registers. Note that it is more efficient to issue a new
write command than to write the default value to more than
two consecutive reserved (or unmapped) registers.
Table 19. Streaming Mode (No Addresses Skipped)
Address Ascension
Stop Sequence
Increment
0x0000 … 0x1FFF
Decrement
0x1FFF … 0x0000
Table 20. Serial Control Port, 16-Bit Instruction Word
MSB
LSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
SCLK DON'T CARE
SDIO
A12
A13
A14
R/W
A11 A10 A9
A8
A7
A6 A5
A4
A3 A2
A1
A0
D7 D6
D5
D4
D3
D2 D1
D0
D7
D6 D5
D4
D3 D2
D1
D0
DON'T CARE
DON'T CARE
DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA
Figure 25. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data
CS
SCLK
SDIO
SDO
REGISTER (N) DATA
16-BIT INSTRUCTION HEADER
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
A12
A13
A14
R/W
A11 A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DON'T CARE
DON'T CARE
DON'T CARE
DON'T
CARE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 26. Serial Control Port Read—MSB First, Address Decrement, Four Bytes of Data
tS
DON'T CARE
DON'T CARE
A14
A13
A12
A11
A10
A9A8A7
A6A5
D4D3
D2D1D0
DON'T CARE
DON'T CARE
R/W
tDS
tDH
tHIGH
tLOW
tCLK
tC
CS
SCLK
SDIO
Figure 27. Timing Diagram for Serial Control Port Write—MSB First



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