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AD9530 Datasheet(PDF) 13 Page - Analog Devices |
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AD9530 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 41 page  Data Sheet AD9530 Rev. 0 | Page 13 of 41 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 DNC VDD OUT2 4 OUT2 5 GND 6 VDD 7 OUT1 TOP VIEW (Not to Scale) AD9530 25 VDD 26 REF_SEL 27 GND 28 REFB 29 REFB 30 VDD 31 GND 32 REFA 33 REFA 34 VDD 35 DNC 36 LF_1 8 OUT1 9 GND 10 GND 11 BP_CAP_3 12 BP_CAP_2 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS. 2. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 2. Pin Configuration Table 16. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 LF_1 O Loop Filter Connection, Negative Output Side of the Active Loop Filter Op Amp. Connect the PLL active loop filter components (R1, C1, and C2) to this pin and LF_2 (Pin 48). 2, 19, 36, 37, 46 DNC N/A Do Not Connect. Do not connect to this pin. 3 VDD P Power Supply for REFA. 4 REFA I Reference Clock Input A. This pin, along with REFA, is the first differential reference input for the PLL. 5 REFA I Complimentary Reference Clock Input A. This pin, along with REFA, is the first differential reference input for the PLL. 6 GND GND Ground for the REFA Power Supply. Connect this pin to ground. 7 VDD P Power Supply for REFB. 8 REFB I Reference Clock Input B. This pin, along with REFB, is the second differential reference input for the PLL. 9 REFB I Complimentary Reference Clock Input B. This pin, along with REFB, is the second differential reference input for the PLL. 10 GND GND Ground for the REFB Power Supply. Connect this pin to ground. 11 REF_SEL I Reference Input Select. This pin is the digital input to select REFA or REFB as the active reference to the PLL. This pin has an internal 75 kΩ pull-up resistor. Logic high (default) selects REFA. Logic low selects REFB. 12 VDD P Power Supply for the Serial Port Interface (SPI) and the PFD. 13 RESET I Chip Reset, Active Low. This pin has an internal 75 kΩ pull-up resistor. 14 SDO O Serial Control Port Unidirectional Serial Data Output. This pin is high impedance during 3-wire SPI mode. 15 SDIO I/O Serial Control Port Bidirectional Serial Data Input/Output. 16 SCLK I Serial Control Port Clock Signal. This pin has an internal 75 kΩ pull-down resistor. 17 CS I Serial Control Port Chip Select, Active Low. This pin has an internal 75 kΩ pull-up resistor. 18 LD O PLL Lock Detect Output. 20 to 23 VDD P 2.5 V Power Supply for the RTWO Internal LDO. 24 BP_CAP_1 O RTWO LDO Op Amp Bypass Capacitor. Connect an external 0.01 µF capacitor from this pin to GND. 25 BP_CAP_2 O RTWO LDO Bypass Capacitor. Connect an external 1 µF capacitor from this pin to GND. 26 BP_CAP_3 O RTWO Bias Supply Bypass Capacitor. This pin can be left unconnected (floating). 27 GND GND Ground for RTWO Power Supply. Connect this pin to ground. 28 GND GND Ground for OUT1 Power Supply. Connect this pin to ground. |
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