AD9530 datasheet(25/41 Pages) AD

25 / 41 page

Data Sheet

AD9530

Rev. 0 | Page 25 of 41

DATA BIT N – 1

DATA BIT N

SCLK

SDIO

SDO

tDV

Figure 28. Timing Diagram for Serial Control Port Register Read—MSB First

SCLK DON'T CARE

DON'T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON'T CARE

A0 A1 A2

A5 A6

A9 A10 A11 A12

R/W

A14

A13

D5 D6

D1 D2

D4 D5

Figure 29. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data

SCLK

SDIO

tHIGH

tLOW

tCLK

tDS

tDH

BIT N

BIT N + 1

Figure 30. Serial Control Port Timing—Write

Table 21. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and the rising edge of SCLK (see Figure 27 and Figure 30)

tDH

Hold time between data and the rising edge of SCLK (see Figure 27 and Figure 30)

tCLK

Period of the clock (see Figure 27 and Figure 30)

Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)

(see Figure 27 and Figure 30)

Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)

(see Figure 27 and Figure 30)

tHIGH

Minimum period that SCLK is in a logic high state (see Figure 27 and Figure 30)

tLOW

Minimum period that SCLK is in a logic low state (see Figure 27 and Figure 30)

tDV

SCLK to valid SDIO (see Figure 28)

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