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AD9530

Data Sheet

Rev. 0 | Page 34 of 41

R DIVIDER CONTROL (REGISTER 0x011)

Table 36. Bit Descriptions for R_DIVIDER_CTRL (Default: 0x06)

Bits

Bit Name

Settings

Description

Default

Access

[7:3]

RESERVED

00000b

When writing to Register 0x011, these bits must be 00000b.

00000b

REFIN_OVERRIDE_PIN_SEL

Reference input override pin selection.

REFIN_INPUT_SEL bit (in this register) controls reference input

selection.

REF_SEL pin controls reference input selection. REFA is selected if

the REF_SEL pin is high. REFB is selected if the REF_SEL pin is low.

REFIN_INPUT_SEL

Reference input selection.

Select REFB input if REFIN_OVERRIDE_PIN_SEL = 0.

Select REFA input if REFIN_OVERRIDE_PIN_SEL = 0.

REFIN_DIV_RESET

Reference input divider reset (autoclearing). Setting this (self

clearing) bit resets the R divider. This bit is live, meaning

IO_UPDATE is not needed for it to take effect.

REFERENCE INPUT A (REGISTER 0x012)

Table 37. Bit Descriptions for REF_A (Default: 0x07)

Bits

Bit Name

Settings

Description

Default

Access

[7:4]

RESERVED

When writing to Register 0x012, these bits must be 0x0

0x0

[3:2]

REFA_TERM_SEL

Reference A input termination select

01b

LVDS mode (100 Ω across the inputs)

DC-coupled mode (50 Ω to ground) (default)

AC-coupled mode (50 Ω to 0.35 V, internal)

DC-coupled high-Z mode

REFA_LDO_EN

Reference A enable LDO

Disabled

Enabled (default)

REFA_EN

Reference A enable

Disabled

Enabled (default)

REFERENCE INPUT B (REGISTER 0x013)

Table 38. Bit Descriptions for REF_B (Default: 0x06)

Bits

Bit Name

Settings

Description

Default

Access

[7:4]

RESERVED

When writing to Register 0x013, these bits must be 0x0

0x0

[3:2]

REFB_TERM_SEL

Reference B input termination select

01b

LVDS mode (100 Ω across the inputs)

DC-coupled mode (50 Ω to ground) (default)

AC-coupled mode (50 Ω to 0.35 V, internal)

DC-coupled high-Z mode

REFB_LDO_EN

Reference B enable LDO

Disabled

Enabled (default)

REFB_EN

Reference B enable

Disabled (default)

Enabled

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