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AD9530 Datasheet(PDF) 29 Page - Analog Devices |
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AD9530 Datasheet(HTML) 29 Page - Analog Devices |
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29 / 41 page  Data Sheet AD9530 Rev. 0 | Page 29 of 41 CONTROL REGISTERS CONTROL REGISTER MAP OVERVIEW Register addresses that are not listed in Table 22 are not used and writing to those registers has no effect. Registers that are marked as reserved must never have their values changed. When writing to registers with bits that are marked reserved, take care to always write the default value for the reserved bits. Unused and reserved registers are in the control register map but are not in the control register description tables. Table 22. Control Register Map Reg. Addr. (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 Default Value (Hex) 0x000 SPI_CONFIGA SOFT_RESET LSB_FIRST ADDRESS_ASCEND SDO_ACTIVE ADDRESS_ ASCEND LSB_FIRST SOFT_RESET 0x00 0x001 SPI_CONFIGB SINGLE_ INSTRUCTION RESERVED READ_BUFFER RESERVED CALIBRATE VCO DIVIDER_RESET RESERVED 0x00 0x002 STATUS PLL_LOCKED SIGNAL_ PRESENT FEEDBACK_OK REFERENCE_ OK RESERVED SLEEP Varies 0x003 CHIP_TYPE RESERVED CHIP_TYPE, Bits[3:0] 0x05 0x004 PRODUCT_ ID[11:0] PRODUCT_ID, Bits[3:0] RESERVED 0x3F 0x005 PRODUCT_ID, Bits[11:4] 0x01 0x006 PART_VERSION PART VERSION 0x14 0x007 RESERVED RESERVED 0x00 0x008 RESERVED RESERVED 0x00 0x009 RESERVED RESERVED 0x00 0x00A USER_ SCRATCHPAD1 USER_SCRATCHPAD1, Bits[7:0] 0x00 0x00B SPI_VERSION SPI_VERSION, Bits[7:0] 0x00 0x00C VENDOR_ID VENDOR_ID, Bits[7:0] 0x56 0x00D VENDOR_ID VENDOR_ID, Bits[15:8] 0x04 0x00E RESERVED RESERVED 0x00 0x00F IO_UPDATE RESERVED IO_UPDATE 0x00 0x010 R_DIVIDER R_DIVIDER, Bits[7:0] 0x01 0x011 R_DIVIDER_ CTRL RESERVED REFIN_OVERRIDE_ PIN_SEL REFIN_INPUT_ SEL REFIN_DIV_ RESET 0x06 0x012 REF_A RESERVED REFA_TERM_SEL REFA_LDO_EN REFA_EN 0x07 0x013 REF_B RESERVED REFB_TERM_SEL REFB_LDO_EN REFB_EN 0x06 0x014 OUT1_DIVIDER OUT1_DIVIDER, Bits[7:0] 0x01 0x015 OUT1_DRIVER_ CONTROL RESERVED OUT1_AMP_TRIM OUT1_TERM_ EN OUT1_LDO_EN OUT1_EN OUT1_ DIVIDER_RESET 0x24 0x016 OUT2_DIVIDER OUT2_DIVIDER, Bits[7:0] 0x01 0x017 OUT2_DRIVER_ CONTROL RESERVED OUT2_AMP_TRIM OUT2_TERM_ EN OUT2_LDO_EN OUT2_EN OUT2_ DIVIDER_RESET 0x24 0x018 OUT3_DIVIDER OUT3_DIVIDER, Bits[7:0] 0x01 0x019 OUT3_DRIVER_ CONTROL RESERVED OUT3_AMP_TRIM OUT3_TERM_ EN OUT3_LDO_EN OUT3_EN OUT3_ DIVIDER_RESET 0x24 0x01A OUT4_DIVIDER OUT4_DIVIDER, Bits[7:0] 0x01 0x01B OUT4_DRIVER_ CONTROL RESERVED OUT4_AMP_TRIM OUT4_TERM_ EN OUT4_LDO_EN OUT4_EN OUT4_ DIVIDER_RESET 0x24 0x01C VCO_POWER RESERVED VCO_LDO_WAIT_ OVERRIDE VCO_POWER 0x01 0x01D PLL_LOCKDET_ CONTROL RESERVED PLL_LOCK_ DET_START PLL_LOCK_DET_ERR_THRESHOLD, Bits[2:0] PLL_LOCK_ DET_RESET 0x0C 0x01E PLL_LOCKDET_ READBACK1 PLL_LOCK_DET_ERROR, Bits[7:0] Varies 0x01F PLL_LOCKDET_ READBACK2 RESERVED PLL_LOCK_ DET_DONE PLL_LOCK_ DET_RANGE PLL_LOCKED PLL_LOCK_DET_ERROR, Bits[9:8] Varies 0x020 M1_DIVIDER RESERVED M1_DIVIDER M1_LDO_EN M1_EN M1_DIVIDER_ RESET 0x16 0x021 M2_DIVIDER RESERVED M2_DIVIDER M2_LDO_EN M2_EN M2_DIVIDER_ RESET 0x16 0x022 M3_DIVIDER RESERVED M3_DIVIDER M3_EN M3_DIVIDER_ RESET 0x02 0x023 N_DIVIDER N_DIVIDER 0x0A |
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