AD9530 datasheet(21/41 Pages) AD

21 / 41 page

Data Sheet

AD9530

Rev. 0 | Page 21 of 41

CML Output Drivers

The AD9530 has four CML output drivers that are operable up to

2.7 GHz. Each output driver must be externally terminated as

shown in the Input/Output Termination Recommendations

section. The output voltage swing, internal termination, and

power-down of each CML driver are configurable by writing to

the appropriate registers. An initial calibration of the internal

termination and voltage swing is performed after a POR event.

This calibration requires that OUT1 is terminated, regardless of

whether the driver is needed in a specific design. A functional

diagram of the output driver is shown in Figure 18.

VDD

50Ω

MN2

18mA TO 24mA

MN3

MN0

MN1

Figure 18. CML Output Simplified Equivalent Circuit

The CML differential voltage (VOD) is selectable from 0.8 V to 1.1 V

via Bits[5:4] of Register 0x015, Register 0x017, Register 0x019,

and Register 0x01B.

The AD9530 has optional internal termination for cases where

transmission line impedance mismatch between the CML output

and the receiver causes increased reflections at high output

frequencies. These terminations improve impedance match

traces at high frequency at the expense of drawing twice as

much current as the default operating condition.

For Register 0x015 (for OUT1), Register 0x017 (for OUT2),

setting the OUTx_TERM_EN (Bit 3) = 1 enables the on-chip

termination and is configurable for each driver.

Each CML output can be enabled as needed by altering the

appropriate OUTx_ENABLE bit.

RESET MODES

The AD9530 has a POR and several other ways to apply a reset

condition to the chip.

Power-On Reset (POR)

During chip power-up, a POR pulse is issued when VDD

reaches ~2 V and restores the chip to the default on-chip

setting. At this point, a 2 sec counter is started to allow all the

user device settings to load and the RTWO to stabilize. After

the 2 sec counter finishes, the user can issue a VCO calibration

and outputs begin toggling ~500 ns later.

2 sec Wait Timer

The 2 sec wait timer ensures that all internal supplies are stable

before allowing the user to issue a VCO calibration. This timer

only starts after a POR. The user may program all the necessary

registers during this time, including the VCO calibration bit. After

the timer times out and a reference input is applied, the

calibration issues, allowing the PLL to lock and the outputs to

toggle. The maximum internal wait time is shown in Table 5.

Hardware Reset via the RESET Pin

Driving the RESET pin to a Logic 0 and then back to a Logic 1

restores the chip to the on-chip default register settings.

Soft Reset via the Serial Port

The serial port control register allows a soft reset by setting

restores to the on-chip default settings, except for Register 0x000

and Register 0x001. Register 0x000 and Register 0x001 retain

the values prior to reset, except for the self clearing bits. However,

the self clearing operation does not complete until an additional

serial port SCLK cycle occurs; the AD9530 is held in reset until

this additional SCLK cycle.

Individual Divider Reset via the Serial Port

Every divider in the AD9530 has the ability to reset individually

by using the appropriate reset bit. This reset does not clear the

value written in the specific divider register but restarts the

divider count to 0, which results in a phase adjustment. See the

associated divider section or the register map for the location of

these bits.

POWER-DOWN MODES

Sleep Mode via the Serial Port

Place the AD9530 in sleep mode by writing Register 0x002,

Bits[1:0] = 11. This mode powers down the following blocks:

•

All OUTx drivers

•

All REFx inputs

•

All Mx dividers

•

RTWO power set to minimum

•

CP current set to minimum

•

PFD

•

Loop filter op amp

Individual Clock Input and Output Power-Down

Power down any of the reference inputs or clock distribution

outputs by individually writing to the appropriate registers. The

each input and output.

AD9530 Datasheet(PDF) 21 Page - Analog Devices

AD9530 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL